Hmm after the 4MB RAM upgrade (8x TMS44400DJ-60 replacing the 8x NEC 424256-10, PLCC MMU A9/MAD9 wire mod per this thread's guidance), the machine shows absolutely no boot signal at all — not even a grey screen. Power LED is on, nothing else happens.
What I've verified so far:
MMU pin 64 (MAD9) confirmed correct by physical pin-counting on the chip itself — no other trace connects to it anywhere else on the board, matches the datasheet
Disconnected the wire between the 33-ohm resistor and MMU pin 64 entirely — still no boot
Also tied that same wire to GND (to avoid a floating input) — still no boot
Measured VCC (pin 13) vs VSS (pin 26) on all 8 new RAM chips while powered — all read 5.09V, correct
Diode-tested pin 5 (A9) against neighboring pins (RAS, W, A0) on all 8 chips — all show ~1k ohm, no shorts
Checked for solder bridges after every single chip installation, repeatedly — found none
All 8 chips oriented correctly (pin 1 markers match silkscreen; also confirmed by correct VCC readings)
Not yet tried: Swapping 1-2 of the new chips back to the original NEC 424256-10 to isolate whether one of the new chips itself is faulty.
Any ideas what else could cause a complete boot failure like this, even with the RAM upgrade wiring fully disconnected/grounded?
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Update — oscilloscope findings
Did a round of scope measurements to narrow this down further. Summary:
RAS (measured at the RAM chips): toggling continuously, regular pattern — consistent with RAS-only refresh cycles
MAD9 (MMU pin 64): toggling normally, looks like proper address multiplexing
CAS (measured both at the RAM chips AND directly at MMU pin 22, CAS1H): permanently HIGH, never asserted — on all 8 chips
DTACK (measured at both CPU pin 10 AND MMU pin 53): permanently HIGH, never asserted
AS (CPU pin 6) is HIGH in steady state, but a video capture of power-on shows ~1 second of dense, active toggling on AS immediately after power-on, then it abruptly stops and stays high from then on
RAM* (MMU pin 33) checked together with AS: both high in steady state (post-hang)
RESET (CPU pin 18) and HALT (CPU pin 17): both normal/inactive, CPU is not held in reset
BR, BG, BGACK: BR/BG stay high (no bus request pending), BGACK shows only minor noise/no clean assertion — doesn't look like DMA is holding the bus
So it looks like the CPU runs for about 1 second post-reset (presumably executing early TOS boot code from ROM), then stops issuing bus cycles entirely. At that point the MMU appears to only ever do RAS-only cycles and never completes a real access (no CAS, no DTACK ever asserted) — even during the ~1s window where AS was clearly active.
This points toward the hang happening right around where TOS would first try to access/test RAM, but doesn't yet tell me whether that's a chip issue, an addressing/bank config issue introduced by the upgrade, or a MMU control-signal issue.
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