Invision ECS faster 32bit uploads

[utri007]

Wondering what this means and would it be doable with TF536, from Picasso 96 wiki

Indi in combination with an ACA500+ now supports faster 32bit uploads into the frame buffer memory if hardware ID $0B is found.

This makes it faster with RTG

https://wiki.icomp.de/wiki/P96#Update_V3.6.0

[alexh]

Wondering what this means

The ACA500+ is a 68000 accelerator with a 16-bit data bus and the Indivision ECS is a re-implementation of the Denise (with extra bits) which also has a 16-bit data bus. There is no way to perform 32-bit writes from CPU->Indivision. What I suspect it means is they have added a 32-bit write cache internally inside the Indivision ECS CPLD which might improve it's RAM bandwidth (writes to RAM would only be every other cycle). This is pure speculation.

if hardware ID $0B is found

I suspect that this is the hardware ID of the newer Indivision ECS V4 firmware (v1.1).

would it be doable with TF536, from Picasso 96 wiki

I suspect this is a feature of newer P96 in conjunction with Indivision ECS V4 firmware (v1.1). Accelerator is almost certainly irrelevant.

[alexh]

Confirmed.

https://eab.abime.net/showpost.php?p=17 ... tcount=844