The original TF536 buffer is a SN74CB3T3245PW (but EOL now) . Problem is, its enable/disable is a bit to slow at 8ns (yes really)
The ones I went to are TI SN74CBTLV3245APWR Faster at 6.4ns, but the oops, not 5V tolerant.
So ideally I need something along those lines bought 5ns or faster, which seems impossible
Other chips have a direction control or dual supply but not having much luck that way either. Direction control I suppose could be possible that it was wise to RW directly, I think RW asserts before AS.. So it shouldn't delay things I think...
It's a bit of a conundrum because the buses are basically multiplex between the ST side bus (5v) and the 3.3V bus on the SDRAM. So the SDRAM buffers always end up seeing 5V from the bus or CPU (im assuming the CPU has week pullups to 5V) But either way, the ROM is there 5V anyway..
Basically needs some sort of solution that can do voltage translation 3.3 V <> 5V and have a very fast propagation and output enable delay.. Propagation delay of the current chips is <1ns so thats fine, but the OE needs to be at most 5ns... I don't think such thing exists
EDIT:
Maybe someone can confirm the CPU can use 3.3V pullups on the databus, maybe it will be simpler if I put the voltage translator on the 16bit bus, and moved the 030 databus to 3.3V only, wire it direct to the SDRAM via 3.3v fast buffers (no translation) ..
EDIT2:
Actually I think SDRAM isolates its own databus anyway ? Otherwise it would be impossible to link it direct to a databus without isolation buffers ?
If the CPU databus can be pulled up to 3.3V then other than the ROM, have the whole 536 databus 3.3V, and put the translation on the 16bit buffer for the 5N ST bus.. would seem a lot easier to do it all that way.
