So introducing the Phoenix BLUE as the new board we are designing to enable us to develop the BL(itter) and (gl)UE chips on the H4/5. This board is a universal board that can be configured with two jumpers and a core to either be a BLITTER or a GLUE chip replacement. I'll be locking the other threads in this area on BLITTER and GLUE development and this will be thread going forward for our BLITTER / GLUE development.
The board is comprised of a Max10 FPGA, 5V <-> 3V3 translators and has a 4x 5V IO pins out for additional connectivity for future development. Its size fits perfectly on each BLITTER and GLUE PLCC location on an H4/5 without intruding on any other component on the board. It's as small as we can get it around that PLCC68 form factor.
Next steps are reviewing the design between @ijor, @exxos and myself before sending off for manufacture. Our first batch is for development of the cores and will be larger version of the FPGA to allow us to debug the cores and test additional features in the future but the main objective is to get the cores running correctly as cycle exact chips on real hardware.
We will keep you updated as to our progress with the Phoenix BLUE.
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