Thought I would do a quick topic on this to show development and what the project is about as I believe there is still some confusion over it all..
The Phoenix Nexus board will be a FPGA plug-in board to fit the H4 / H5 series motherboards to replace the blitter, GLUE, MMU with FPGA cores.
The project branches from the other thread such as recreating the chips in FPGA . @Icky and @ijor are currently working on finishing the testing of the cores individually to make sure we have a totally accurate individual core.
I feel this work is important as only combined cores exist in other projects such as the MiST. But these are not really full cores which will "drop in" to a original machine and work. So we aim to have true cycle accurate cores very soon.
BLITTER
viewtopic.php?f=80&t=79
GLUE
viewtopic.php?t=7338
viewtopic.php?t=2536
MMU
viewtopic.php?t=2478
viewtopic.php?t=7312
Early work was using the Suska cores (with Wolfgang's permission) but we ran into various issues where later @ijor took over to develop better cores for the project.
Its aim is to replace the blitter (or simply add a blitter as they are hard to find and expensive) with a higher speed version with the possibility of adding more features at a later date. We can run the blitter at even higher speeds than the CPU. This not only does blitting many times faster, it will reduce the "hog time" of the bus giving the CPU more time to do stuff as well.
The original MMU wasn't stable with the "double overclock" which lead me to abandon that direction completely. More so as it will be a lot of work in solving all the problems just to basically hit a brick wall because there is simply no "whats next" aspect to it. It's essentially a dead-end project right from the start. So recreating the MMU means we can fix all the issues while aiming to remain fully backwards compatible and cycle accurate with the original chips.
The good thing is that we can inherently run these cores at almost any speed we want. The first step of the project is to simply replace the three main chips and run them at stock speed. The second phase of the project is to run 16MHz (likely with the motherboard simm) and later push to 32MHz bus with onboard SDRAM.
The main bottleneck in any ST system is always switching back to 8MHz to access the ST side stuff such as video RAM etc. It's why accelerators have "TTram" as the CPU can access that RAM at 50MHz or whatever. However, performance is crippled with anything which is having to access STram or video RAM. So the aim of the new chipset is to remove that limitation and simply have a faster bus of 32MHz.
Because we are recreating the chips, we can fix the 4MB STram limit and go for 12MB for example. We can fix DMA issues , including the blitters current limitation of 4MB memory access. We can simply fix everything and do things properly. No need for endless hacks with everything!
The faster bus opens the door to more "video bandwidth". This means higher resolutions or colour depths are possible with the reworked shifter. Is no need to hack on graphics cards or whatever, it will all be a evolution of the original ST design.
I certainly believe exciting times are in the near future :)
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Phoenix Nexus FPGA board
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exxos
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exxos
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Re: Phoenix Nexus FPGA board
Sneak preview of what the board will look like...
The two white squares will actually be holes in the PCB to allow access to the CPU and ROM on the motherboard...
I'm yet to think of a name for the new MMU..
The two white squares will actually be holes in the PCB to allow access to the CPU and ROM on the motherboard...
I'm yet to think of a name for the new MMU..
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atari030
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Re: Phoenix Nexus FPGA board
I'm astounded at the amount of Atari goodness being trotted out atm. I can't keep up.
How's enhanced MMU/eMMU for a name? Very Australian.
How's enhanced MMU/eMMU for a name? Very Australian.
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dml
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Re: Phoenix Nexus FPGA board
Chip names?
Nicky, Nijor & Nexx :hide: :yay2:
d:m:l
BadMooD d/l: https://www.leonik.net/dml/sec_bm.py
SVO30 d/l: https://www.leonik.net/dml/sec_svo30.py
Q2 engine d/l: https://www.leonik.net/dml/sec_q2.py
AGT project: https://www.leonik.net/dml/sec_agt.py
Atari page: http://www.leonik.net/dml/sec_atari.py
YT: https://www.youtube.com/@dmlTPT
BadMooD d/l: https://www.leonik.net/dml/sec_bm.py
SVO30 d/l: https://www.leonik.net/dml/sec_svo30.py
Q2 engine d/l: https://www.leonik.net/dml/sec_q2.py
AGT project: https://www.leonik.net/dml/sec_agt.py
Atari page: http://www.leonik.net/dml/sec_atari.py
YT: https://www.youtube.com/@dmlTPT
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PhilC
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Re: Phoenix Nexus FPGA board
nah, Bungle, Zippy and George.
If it ain't broke, test it to Destruction.
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mrbombermillzy
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Re: Phoenix Nexus FPGA board
BITD, they would probably be named after a female office secretary/member of staff. :)
Perhaps in this instance, the subject could be mythical creatures?
Phoenix....unicorn/hydra/minotaur/siren/medusa/pegasus/etc... ?
Perhaps in this instance, the subject could be mythical creatures?
Phoenix....unicorn/hydra/minotaur/siren/medusa/pegasus/etc... ?
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DoG
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Re: Phoenix Nexus FPGA board
Good names although a few already exist as Atari hardware periferals, like hydra (cartridge for network), unicorn (USB host controller for ACSI), Medusa (Atari computer and a hdmi/scart scandoubler).mrbombermillzy wrote: 12 Jul 2025 10:28 Phoenix....unicorn/hydra/minotaur/siren/medusa/pegasus/etc... ?
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dml
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Re: Phoenix Nexus FPGA board
ROFL!
d:m:l
BadMooD d/l: https://www.leonik.net/dml/sec_bm.py
SVO30 d/l: https://www.leonik.net/dml/sec_svo30.py
Q2 engine d/l: https://www.leonik.net/dml/sec_q2.py
AGT project: https://www.leonik.net/dml/sec_agt.py
Atari page: http://www.leonik.net/dml/sec_atari.py
YT: https://www.youtube.com/@dmlTPT
BadMooD d/l: https://www.leonik.net/dml/sec_bm.py
SVO30 d/l: https://www.leonik.net/dml/sec_svo30.py
Q2 engine d/l: https://www.leonik.net/dml/sec_q2.py
AGT project: https://www.leonik.net/dml/sec_agt.py
Atari page: http://www.leonik.net/dml/sec_atari.py
YT: https://www.youtube.com/@dmlTPT
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mrbombermillzy
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Re: Phoenix Nexus FPGA board
Yeah, I know. I realised as soon as I was writing out the names. Was hoping someone would break out a book on Greek mythology to look for some lesser known beasts! :)DoG wrote: 12 Jul 2025 11:22Good names although a few already exist as Atari hardware periferals, like hydra (cartridge for network), unicorn (USB host controller for ACSI), Medusa (Atari computer and a hdmi/scart scandoubler).mrbombermillzy wrote: 12 Jul 2025 10:28 Phoenix....unicorn/hydra/minotaur/siren/medusa/pegasus/etc... ?
Although saying that, I think Minotaur would be good for a shifter or blitter....
I remember the old Sinbad film (with the Ray Harryhausen animatronic monsters) which had the golden Minotaur.
That thing didnt muck about. It was strong, silent and just got on with the job, shifting blocks and stuff like that until it could do so no more. You couldnt ask for any more. :lol:
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exxos
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- Location: UK
Re: Phoenix Nexus FPGA board
- Mega MMU - Matches the scale of "Hyper" and "Super," evoking a powerful, enhanced memory management unit.
- Ultra MMU - Suggests cutting-edge, superior performance, fitting the retro-tech vibe.
- Giga MMU - Implies massive capability, aligning with the theme of enhanced components.
- Turbo MMU - Conveys high-speed performance, consistent with the "Hyper" naming style.
- Quantum MMU - Evokes advanced, next-level technology for a superior MMU.
- Mighty MMU - Suggests strength and power, emphasizing a robust memory management unit.
- Maxi MMU - Implies maximum performance and improvement over the original MMU.
- Master MMU - Conveys control and superiority, positioning it as the ultimate MMU.
- OmniMMU - Suggests an all-encompassing, powerful memory management unit with "MMU" embedded.
- TurboMMU - Implies high-speed, enhanced performance with "MMU" in the name.
- QuantumMMU - Evokes cutting-edge, superior technology with "MMU" integrated.
- Gimmu - A playful, compact name implying a robust, gimmick-free MMU with "MMU" embedded.
- DynaMMU - Short for "Dynamic MMU," suggesting adaptability and power with "MMU" in the name.
- Immu - Suggests an improved or immutable MMU, sleek and modern with "MMU" embedded.
- Ammuntion - Derived from "ammunition," suggesting firepower and strength with "MMU" in the sequence.
- Immunity - Implies a robust, unassailable memory management unit with "MMU" embedded.
- Summum - From Latin "summum" (highest), conveying top-tier performance with "MMU" in the name.
- Commune - Suggests a unified, efficient memory system with "MMU" embedded.
- Emmulate - A play on "emulate," hinting at replicating and enhancing MMU functions with "MMU" in the sequence.
- Gimmux - A techy blend implying a straightforward, powerful MMU with "MMU" in the middle.
- OptiMMU - Suggests optimized, superior memory management with "MMU" embedded.
- PriMMU - Derived from "prime," implying top-tier, best-in-class performance with "MMU" in the name.
- SupreMMU - Evokes supremacy, aligning with the "Super" theme and containing "MMU."
- MaxiMMU - Indicates maximum improvement and capability with "MMU" embedded (repeated for emphasis on superiority).
- EpiMMU - From "epic" or "epitome," suggesting the ultimate MMU with "MMU" in the name.
- SummaMMU - Inspired by "summum" (Latin for highest), conveying peak performance with "MMU" embedded.
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