Help: PAL TO GAL

[Robson]

Hi,

Can I get some help converting the attached .bin files (from PAL16L8) to jedec I can burn into GAL16V8A?
I couldn't get an error free conversion out of them.

Attached whatever is available for this, nothing more.

Or even better if it is possible to burn 2x PAL16L8s (My programmer can't deal with them) I can send them to you, covering all costs, etc.

I'm stuck, so everything would be helpful at this point.

Thanks.
Robson

[6502addict]

Recently Ia asked a IA engine (Claude Sonnet) to reverse engineer a GAL from the jedec ?
it produced an Abel File, A Wincupl file and even a source in VHDL

perhaps that you can reverse engineer your PAL
and from the wincupl burn a suitable GAL

[6502addict]

your BI-O.bin in wincupl

Name BI_IO;
PartNo 00;
Date 16/03/2025;
Revision 01;
Designer Engineer;
Company Vintage Computer;
Assembly None;
Location None;
Device G16V8;

/* *************** INPUT PINS *********************/
PIN 1 = A0; /* Address bit 0 */
PIN 2 = A1; /* Address bit 1 */
PIN 3 = A2; /* Address bit 2 */
PIN 4 = A3; /* Address bit 3 */
PIN 5 = A4; /* Address bit 4 */
PIN 6 = A5; /* Address bit 5 */
PIN 7 = A6; /* Address bit 6 */
PIN 8 = A7; /* Address bit 7 */
PIN 9 = DIR; /* Direction control (0=read, 1=write) */
PIN 11 = !CS; /* Chip Select (active low) */

/* *************** OUTPUT PINS *********************/
PIN 12 = IO0; /* Bidirectional I/O bit 0 */
PIN 13 = IO1; /* Bidirectional I/O bit 1 */
PIN 14 = IO2; /* Bidirectional I/O bit 2 */
PIN 15 = IO3; /* Bidirectional I/O bit 3 */
PIN 16 = IO4; /* Bidirectional I/O bit 4 */
PIN 17 = IO5; /* Bidirectional I/O bit 5 */
PIN 18 = IO6; /* Bidirectional I/O bit 6 */
PIN 19 = IO7; /* Bidirectional I/O bit 7 */

/* Define operations */
READ = !DIR & !CS; /* Read operation when DIR=0 and CS active */
WRITE = DIR & !CS; /* Write operation when DIR=1 and CS active */

/* Define output enables */
IO0.OE = READ # WRITE; /* Enable I/O when either reading or writing */
IO1.OE = READ # WRITE;
IO2.OE = READ # WRITE;
IO3.OE = READ # WRITE;
IO4.OE = READ # WRITE;
IO5.OE = READ # WRITE;
IO6.OE = READ # WRITE;
IO7.OE = READ # WRITE;

/* Logic equations */
/* In read mode, I/O pins get address bus values */
IO0 = A0 & READ;
IO1 = A1 & READ;
IO2 = A2 & READ;
IO3 = A3 & READ;
IO4 = A4 & READ;
IO5 = A5 & READ;
IO6 = A6 & READ;
IO7 = A7 & READ;

/* In write mode, I/O pins are controlled externally *

your BI-O.bin in vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity BI_IO is
Port (
A : in STD_LOGIC_VECTOR(7 downto 0); -- Address bus
DIR : in STD_LOGIC; -- Direction control (0=read, 1=write)
nCS : in STD_LOGIC; -- Chip select (active low)
IO : inout STD_LOGIC_VECTOR(7 downto 0) -- Bidirectional I/O
);
end BI_IO;

architecture Behavioral of BI_IO is
signal READ : STD_LOGIC;
signal WRITE : STD_LOGIC;
begin
-- Define control signals
READ <= '1' when (DIR = '0' and nCS = '0') else '0';
WRITE <= '1' when (DIR = '1' and nCS = '0') else '0';

-- Bidirectional I/O control
-- In READ mode (DIR=0), drive data from address bus to I/O pins
-- In WRITE mode (DIR=1), I/O pins are inputs (data flows from external sources)
IO <= A when READ = '1' else (others => 'Z');

-- Note: No need to explicitly handle external data coming in during WRITE mode
-- as the tri-state operation handles this automatically
end Behavioral;

your BI-MEM in WINCUPL
Name BI_MEM;
PartNo 00;
Date 16/03/2025;
Revision 01;
Designer Engineer;
Company Vintage Computer;
Assembly None;
Location None;
Device G16V8;

/* *************** INPUT PINS *********************/
PIN 1 = A15; /* Address bit 15 */
PIN 2 = A14; /* Address bit 14 */
PIN 3 = A13; /* Address bit 13 */
PIN 4 = A12; /* Address bit 12 */
PIN 5 = A11; /* Address bit 11 */
PIN 6 = A10; /* Address bit 10 */
PIN 7 = A9; /* Address bit 9 */
PIN 8 = A8; /* Address bit 8 */
PIN 9 = !MREQ; /* Memory request (active low) */
PIN 10 = !RD; /* Read signal (active low) */
PIN 11 = !WR; /* Write signal (active low) */

/* *************** OUTPUT PINS *********************/
PIN 12 = !ROM_CS; /* ROM Chip Select (active low) */
PIN 13 = !RAM_CS; /* RAM Chip Select (active low) */
PIN 14 = !ROM_OE; /* ROM Output Enable (active low) */
PIN 15 = !ROM_WE; /* ROM Write Enable (active low) */
PIN 16 = !RAM_OE; /* RAM Output Enable (active low) */
PIN 17 = !RAM_WE; /* RAM Write Enable (active low) */
PIN 19 = !MEMEN; /* Memory Enable (active low) */

/* Define memory regions */
FIELD ADDRESS = [A15..A8];

/* Define memory map:
ROM: 0x0000-0x7FFF (32KB)
RAM: 0x8000-0xFFFF (32KB)
*/
ROM_REGION = !A15; /* ROM is in lower half of memory space */
RAM_REGION = A15; /* RAM is in upper half of memory space */

/* Define operation types */
READ = !MREQ & !RD; /* Read operation active */
WRITE = !MREQ & !WR; /* Write operation active */

/* Memory chip select logic */
ROM_CS = ROM_REGION & !MREQ; /* ROM selected when in ROM region & MREQ active */
RAM_CS = RAM_REGION & !MREQ; /* RAM selected when in RAM region & MREQ active */

/* Memory control signals */
ROM_OE = ROM_REGION & READ; /* ROM output enable during reads from ROM region */
ROM_WE = ROM_REGION & WRITE; /* ROM write enable during writes to ROM region */
RAM_OE = RAM_REGION & READ; /* RAM output enable during reads from RAM region */
RAM_WE = RAM_REGION & WRITE; /* RAM write enable during writes to RAM region */

/* Global memory enable signal */
MEMEN = !MREQ; /* Memory enabled when MREQ is active */

your BI-MEM in VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity BI_MEM is
Port (
A : in STD_LOGIC_VECTOR(15 downto 8); -- High address bits
nMREQ : in STD_LOGIC; -- Memory request (active low)
nRD : in STD_LOGIC; -- Read signal (active low)
nWR : in STD_LOGIC; -- Write signal (active low)
nROM_CS : out STD_LOGIC; -- ROM chip select (active low)
nRAM_CS : out STD_LOGIC; -- RAM chip select (active low)
nROM_OE : out STD_LOGIC; -- ROM output enable (active low)
nROM_WE : out STD_LOGIC; -- ROM write enable (active low)
nRAM_OE : out STD_LOGIC; -- RAM output enable (active low)
nRAM_WE : out STD_LOGIC; -- RAM write enable (active low)
nMEMEN : out STD_LOGIC -- Memory enable (active low)
);
end BI_MEM;

architecture Behavioral of BI_MEM is
-- Memory region signals
signal ROM_REGION : STD_LOGIC;
signal RAM_REGION : STD_LOGIC;

-- Operation type signals
signal READ : STD_LOGIC;
signal WRITE : STD_LOGIC;
begin
-- Define memory regions based on address space
-- ROM: 0x0000-0x7FFF (32KB)
-- RAM: 0x8000-0xFFFF (32KB)
ROM_REGION <= not A(15); -- ROM is in lower half of memory space
RAM_REGION <= A(15); -- RAM is in upper half of memory space

-- Define operation types
READ <= '1' when (nMREQ = '0' and nRD = '0') else '0';
WRITE <= '1' when (nMREQ = '0' and nWR = '0') else '0';

-- Memory chip select logic
nROM_CS <= '0' when (ROM_REGION = '1' and nMREQ = '0') else '1';
nRAM_CS <= '0' when (RAM_REGION = '1' and nMREQ = '0') else '1';

-- Memory control signals
nROM_OE <= '0' when (ROM_REGION = '1' and READ = '1') else '1';
nROM_WE <= '0' when (ROM_REGION = '1' and WRITE = '1') else '1';
nRAM_OE <= '0' when (RAM_REGION = '1' and READ = '1') else '1';
nRAM_WE <= '0' when (RAM_REGION = '1' and WRITE = '1') else '1';

-- Global memory enable
nMEMEN <= nMREQ; -- Memory enabled when MREQ is active
end Behavioral;

if you don't find anybody near you I can burn them

[Robson]

Thank you for the quick reply.

Pin 10 can't be RD or any function since it's gnd.
(BI-MEM)
"PIN 10 = !RD; /* Read signal (active low) */"

These are the functions.

Untitled.png

The python script gives me this output.

BI-MEM.bin
==========
SRAM_DTACK = CE_SRAM_O * /XAS +
CE_SRAM_E * /XAS
CE_SRAM_O = A23 * A22 * A21 * A20 * A19 * A18 * /A17 * /A16 * /XAS * XDMA * /XLDS
CE_SRAM_E = A23 * A22 * A21 * A20 * A19 * A18 * /A17 * /A16 * /XAS * XDMA * /XUDS
CE_EPROM = /XROM3 +
/XROM4

BI-IO.bin
=========
/CE_U13_EEPROM = A15 * /A14 * A13 * /A12 * /A11 * A10 * /A9 * /A8 * RXW * /XDEV * /XLDS
/CE_U8_DX2 = A15 * /A14 * /A13 * /A12 * /A11 * /A10 * /A9 * /A8 * /RXW * /XDEV * /XUDS
/CE_U7_DX1 = A15 * /A14 * /A13 * /A12 * /A11 * /A10 * /A9 * /A8 * /RXW * /XDEV * /XLDS
/CE_U6_DIP = A15 * /A14 * A13 * /A12 * /A11 * A10 * /A9 * A8 * RXW * /XDEV * /XLDS
/CE_U12_LED = A15 * /A14 * A13 * /A12 * /A11 * A10 * /A9 * /A8 * /RXW * /XDEV * /XLDS
IO_DTACK = A15 * /A14 * A13 * /A12 * /A11 * A10 * /A9 * /A8 * /XDEV * /XLDS +
/CE_U6_DIP

[alexh]

The problem with AI for files like this is they lie. They say they can convert them and spit out files that look viable, sometimes they even assemble but they are not logically correct.

The problem is there are just not enough example CUPL / AHDL to train correctly

[Robson]

I used AI to generate the pld files, then manually corrected them to the above pinout and added comments to take those lines out. I assume the script runs fine so funcions won't change. I fed these 2 files to Wincupl to generate the jedec files.
I had to change the device to G16V8A though since PAL16L8 is not available in the Wincupl library (it gives an error if I use PAL16L8).

Am I doing the right thing?

Thanks.

BI-IO
/*TITLE 'BI-IO Logic'*/
DEVICE G16V8A;

/*DECLARATIONS*/
PIN 1 = A15;
PIN 2 = A14;
PIN 3 = A13;
PIN 4 = A12;
PIN 5 = A11;
PIN 6 = A10;
PIN 7 = XDEV;
PIN 8 = XUDS;
PIN 9 = XLDS;
PIN 10 = GND;
PIN 11 = RXW;
PIN 12 = CE_U13_EEPROM;
PIN 13 = CE_U8_DX2;
PIN 14 = CE_U7_DX1;
PIN 15 = CE_U6_DIP;
PIN 16 = CE_U12_LED;
PIN 17 = A8;
PIN 18 = A9;
PIN 19 = IO_DTACK;
PIN 20 = VCC;

/*EQUATIONS*/
IO_DTACK = A15 & !A14 & A13 & !A12 & !A11 & A10 & !A9 & !A8 & !XDEV & !XLDS # !CE_U6_DIP;
CE_U13_EEPROM = A15 & !A14 & A13 & !A12 & !A11 & A10 & !A9 & !A8 & RXW & !XDEV & !XLDS;
CE_U8_DX2 = A15 & !A14 & !A13 & !A12 & !A11 & !A10 & !A9 & !A8 & !RXW & !XDEV & !XUDS;
CE_U7_DX1 = A15 & !A14 & !A13 & !A12 & !A11 & !A10 & !A9 & !A8 & !RXW & !XDEV & !XLDS;
CE_U6_DIP = A15 & !A14 & A13 & !A12 & !A11 & A10 & !A9 & A8 & RXW & !XDEV & !XLDS;
CE_U12_LED = A15 & !A14 & A13 & !A12 & !A11 & A10 & !A9 & !A8 & !RXW & !XDEV & !XLDS;

/*END*/


BI-MEM

/*TITLE 'BI-MEM Logic'*/
DEVICE G16V8A;

/*DECLARATIONS*/
PIN 1 = A23;
PIN 2 = A22;
PIN 3 = A21;
PIN 4 = A20;
PIN 5 = A19;
PIN 6 = A18;
PIN 7 = A17;
PIN 8 = A16;
PIN 9 = XROM4;
PIN 10 = GND;
PIN 11 = XROM3;
PIN 12 = SRAM_DTACK;
PIN 13 = XUDS;
PIN 14 = XLDS;
PIN 15 = XDMA;
PIN 16 = XAS;
PIN 17 = CE_SRAM_O;
PIN 18 = CE_SRAM_E;
PIN 19 = CE_EPROM;
PIN 20 = VCC;

/*EQUATIONS*/
SRAM_DTACK = CE_SRAM_O & !XAS # CE_SRAM_E & !XAS;
CE_SRAM_O = A23 & A22 & A21 & A20 & A19 & A18 & !A17 & !A16 & !XAS & XDMA & !XLDS;
CE_SRAM_E = A23 & A22 & A21 & A20 & A19 & A18 & !A17 & !A16 & !XAS & XDMA & !XUDS;
CE_EPROM = !XROM3 # !XROM4;

/*END*/


Thanks.

[alexh]

To find out if it is actually working try a binary where you have the source code. See if it will reproduce identical code

[Robson]

I've managed to do a lot of research/sweating/swearing/testing and finally got it working.
Also, the srcipt's outputs were not 100% accurate so it was good to be able to test them here immediately.

But the main thing is that the result is a fully working STBook test cart (based on sarnau's project - with a redesigned connector and basically a redraw the whole thing).

In action( a bit long video - I missed that it was waiting for me to bypass the errors).