ST DMA chip FIFO buffers

[ijor]

One of the most interesting aspects of the DMA chip, is perhaps the implementation of the FIFO buffers. Below is a small document describing the FIFO control logic that is much more complex than one would expect.

ST DMA chip FIFO buffers.pdf

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Note that the complex control logic and the very unusual shifting sequence described on the document might be considered mostly a curiosity. It doesn’t seem to be relevant externally to the chip, and it doesn’t seem to be something that can be exploited by software in anyway. This is mainly because the DMA chip doesn’t flush a FIFO buffer until it’s completely filled, and also because changing the DMA direction performs a complete reset of the buffers.

[sporniket]

Great work, thank you for the explaination

[12-MHz]

ST DMA chip FIFO buffers.pdf

Ijor, what you're describing about the internal structure is a guess, right?
Or did you really measure it on the chip?

Best regards
Robert

[ijor]

Ijor, what you're describing about the internal structure is a guess, right?
Or did you really measure it on the chip?

It's not a guess. I'm not sure what exactly do you mean by "measure". But yes, I looked inside the chip using die micro photographs to analyze the internal logic.

The only thing that it's a rough estimate is the asynchronous timing. As described in the note the logic is based on internal delays. I don't know for sure how much is the exact delays produced by internal gates, such as an inverter propagation delay. That means that the simulation waveforms are probably not to scale. But it doesn't matter too much here. What matters is that some signals have much more delay than other signals and this creates pulses. What is the exact width of those pulses, I don't know. But again, it doesn't matter too much.