WTB: SEC 68000 Booster?

[mrbombermillzy]

Seeing as it looks like Im going to be coding some gaming/library framework, I was looking to support the SEC 68k booster, just in case Exxos decides to continue in that direction at some point.

Are there any out in the wild that someone is no longer using and wants to get rid of? :)

[DoG]

Can you provide a link to what booster it is?

[PhilC]

@mrbombermillzy as far as I know it was just myself @Icky and @exxos who had one.

[mrbombermillzy]

Oh, I was under the impression a few beta boards made it to the shop?

(I seem to remember seeing a photo of a whole bunch of boards that Exxos posted).

I must have been mistaken then. Sorry.

[PhilC]

@mrbombermillzy I'm happy to dig it out and give it to you but its an unfinished booster, I think it was 64mhz that I got mine to run at.

[exxos]

Other than a couple of prototypes which people had that was as far as it went..

The booster needed 64MHZ ROM which I was last worknig on... BUT the H5 bus couldn't be driven that fast, hence all the isolation buffers..
viewtopic.php?p=85249#p85249 Then lack of time happened...

I don't consider the project abandoned,but I find it unlikely that it will be finished any time soon. I'm more interested in the replacement chipset for the H5 which can be run faster, that would be a lot more "interesting" than a booster. The SEC CPU may ultimately find its way onto a future motherboard revisions, maybe even running at a 64MHz bus, but we are some years away from getting that far yet. I haven't had time in the past 4+ years to even finish the H5 add-ons flashy-clock and Trudie...

[mrbombermillzy]

@mrbombermillzy I'm happy to dig it out and give it to you but its an unfinished booster, I think it was 64mhz that I got mine to run at.

If you have no further use for it and want to get rid to let me tinker then thanks. Im sure I have something you want. :)

Was there much S-RAM/Alt-RAM on it? Do you recall?

@exxos

Well, thats fair enough really. I was just looking to see if I could come up with anything interesting that can be fed back. :D

However, (while we are here and more or less on topic) whenever you posted info about these type of matters, you were always pushing the idea of bringing the bus speeds up on the H5 and that is where you would rather concentrate efforts, rather than faster CPU speeds.

I see you quoted trying 64Mhz bus speeds above.

Im quite aware like with most systems in general, the CPU with its own local faster bus and some RAM is the normal speed boosting solution, as the rest of the system chips will generally fail much past their standard speeds.

Im not a HW/electronics guru, so bear with me if I havent got this, but does your plan entail using clock dividers/buffers to keep all the rest of the system at their regular speeds and (I suppose) designing faster speed versions of e.g. blitter/shifter?

Is that the general plan for the H5?

FYI:

Im currently planning a software implementation method which involves a TF536 card doing most of its processing in isolation, within its own TT-RAM,. If the SEC booster has a decent sized cache RAM, I could possibly model a similar system at the same time. Hence the interest.

.

[exxos]

@mrbombermillzy It only has a 68K CPU nothing else. The main issues came from that every time you went faster, I ran into something else on the ST tripping up. So it took a hell of a lot of time to work though all the problems. ROM speed was the bottleneck as it had to have waitsteates. So its not really any faster than the STE V1 booster currently. The bus couldn't be driven at higher speeds as the rise and fall times were like 40ns.. to slow. Its why I had to isolate the bus in the later revision HERE..

The new board had fast-ram and a 256K fast rom, so ROM would be copied to that 256K RAM on power up, then the system would use the "ROM in RAM" instead of the EPROM which is speed limited. This will allow ROM to be accessed at full speed, without waitstates, similar with the fast-ram. But just ran out of time to work on it all.

Benchmarks
viewtopic.php?f=42&t=2703

Install page.
viewtopic.php?f=82&t=1957

The H5 will have a faster bus, not 8MHz with a 32MHz CPU like boosters normally have. It will be a full 32MHz bus with some other tweaks to gain extra speed from the blitter etc as well.

Its also why I am not in any hurry to finish the SEC booster because like I keep saying, accelerators are all basically obsolete when the new H5 FPGA board is done. TTram becomes obsolete also along with all its "problems". I just want to get rid of all the "hacks" to get stuff done and build the system properly from the ground up.

Ultimately it can have a 030 CPU added with very little "patch logic" as the ST chipset will be built properly and run at higher speeds. So clock switching is not needed. Maybe one day we can adapt for a full 32bit bus.. . The only limit in all this is basically time..... But again, my time is of the drastic reduction because my RSI.. So if people thought things were running slow before getting things done, it's even worse now..

[mrbombermillzy]

Well, thanks for taking the time to explain.

I guess then the bus isolated version (prototype 1E2) with the onboard fast RAM/ROM I was thinking of never made it out to production.

I must be going mad in my older age, I can remember seeing a picture you posted of lots of boards with what I believe was static RAM chips on them, which I was under the impression was for a Mega STE style CPU cache board. Who knows then? :lol:

[Badwolf]

Anyone know a decent source of 68SEC000s?

I was thinking it might be an easier case fit for a new rev DSTB1.

BW