MMU - What does it require to operate?

[stephen_usher]

Given @asapreta 's issue with his machine I thought it a good idea to spin out another thread discussing what the MMU requires to function.

Looking at the schematic it seems that almost all the connections are outputs and that maybe all the chip needs is power and the 16MHz clock signal from the SHIFTER after coming out of reset. At this point it should start the RAM refresh and listen to the address bus.

Are the /RAM, /DEV and /DMA pins inputs or outputs? What about /DE and /LOAD? I'm guessing that those two control the Shifter telling it when to read the data lines for display output. Is VSYNC generated by the MMU or the GLUE?

This sort of information would be useful for any diagnostics.

Similar functional information for the GLUE would be helpful as well.

[ijor]

I'll try to elaborate later, but a quick answer to the specific questions about the function of some of the MMU signals.

Are the /RAM, /DEV and /DMA pins inputs or outputs?

Those are all GLUE outputs. They work like some kind of chip select, if you want. They indicate to MMU which type of bus cycle is being performed. A RAM access, an I/O access, or a DMA one.

What about /DE and /LOAD? I'm guessing that those two control the Shifter telling it when to read the data lines for display output. Is VSYNC generated by the MMU or the GLUE?

DE and VSYNC are also generated by GLUE as part of GLUE's video timing logic. DE means display enable. While DE is active MMU performs video RAM cycles. Yes, LOAD is a strobe generated by MMU for SHIFTER to signal the video ram cycle.

VSYNC is used by MMU only for resetting the video pointer to the video base.

[mrbombermillzy]

While I have nothing to add HW wise, I commend this topic as a way for people (like myself who dont generally deal with ST HW diagnosis) to learn more about the ST system operation without browsing over schematics.

I always enjoyed the long long threads over at AF about blitter timigs/wakestates/shifter specifics, and now hopefully the MMU can be laid bare.

This could help strike up answers/solutions/options for guys making the remakes too.

Keep it up!

[stephen_usher]

Thanks @ijor very useful to know. I've not seen the functional description of the chips written anywhere, and especially not which are inputs and outputs.