Overall problem with the clock patches, is that there are so many different designs, it's difficult to figure out why what was done for what reason.
If we stick with the Atari fixes, they seem to go from noninverting (AND) to inverting, back to noninverting according to https://mikrosk.github.io/clockpatch/
Czuba (creator of the CT60) advocates no clock patch whatsoever, which insinuates signals must be in phase.
The majority of clock patches seems to be based on the popular one of using the inverter 74F04 which then branch off into various bus accelerator designs. It is a contradiction to what Czuba is advocating for the CT60. But I personally have never found any issues yet of using a inverter or buffer style clock patch with the CT60.
If we assume "Variant 1.3" is the "best" baseline version by Atari. It illustrates that EXP & SDMA clock is linked and is insinuating that they be as close in sync as possible. This is not so simple because there is a inherent 4ns delay to the SDMA because of trace impedances etc. So the SDMA will always lag behind any other clock by 4ns. This is also aggravated by the addition of the 150pf caps on some bus accelerators and using inverters which skew 180deg anyway.
On Variant 1.1 @mikro states..
I don't know if this was ever verified in any way ?DoIt F030 claims this schematic is broken and warns the reader that this discrepancy between the CPU clock and others would result in non-working Falcon, “surely with a 060 CPU”. There’s a proposed change to use AND gates for all three signals.
If there was any truth to this, then it would advocate again, that all the signals must be perfectly in phase. Though I have never witnessed any problems with my CT60e relating to any use of any of my clock patches yet. It is possible that information is old and no longer relevant with current CT60 builds ?
I'm going to completely ignore all the versions relating to bus accelerators, in particular any clock patches using inverters as I cannot really see any reason to use inverters other than Atari seriously screwed up something design of the Falcon, though I have not yet seen any evidence to advocate using inverters over buffers in general use yet. My only thought currently is that maybe the inverters at the time had higher output currents and the general buffers were not as good at the time. Though I have not really looked into the hypothesis much either.
The overall summary of all the above assumptions and information, results in version V5.1 clock patch by myself. This time it uses a PLL to sync the clocks to the combel clock precisely. The problem here is that, again, there is a inherent 4ns delay to the SDMA clock. So the V5.1 advances the clock to the SDMA, so after the transmission delay, the SDMA clock precisely in sync with the CPU/EXP clocks. This is presumably what Atari was aiming for the timings of the chipset. This way it keeps the timing as insinuated by Czuba with the CT60, and it also buffers the clocks to solve the SDMA related issues. The best of both worlds so to speak.
So I will make the bottom line assumption ,that Atari when they designed the Falcon, that the intention was to have all the clocks in sync. It failed because of the bad clock drive to the SDMA which resulted in various issues and added a small delay, likely adding additional issues . Possibly then, because of the inherent 4ns delay on the SDMA clock, buffering added more delay and screwed up enough to break the SDMA timing totally. So then the only option would be to use inverters..
I certainly cannot say this will be any better or worse than my V3/V4 designs as I have never seen any issues personally relating to EXP/CPU/SDMA clock timings. The general notion of the clock patches is to buffer the SDMA clock to prevent issues. Though why Atari kept seemingly changing the design all the time, remains somewhat of a mystery. Though again, the V5 goes in a different direction totally in using a PLL which no other design has tried yet. So if we have all the clocks in phase, and bufferd, that *should* be the best .....................


