two IDE adapters inside ST

[LarryL]

Hi,

for my "H5 STX" I am looking for ways to:
1.) configure IDE as 2nd IDE adapter, and/or
2.) deactivate IDE via a jumper

I have seen such possibilities in @agralund realisation of a Blitter/TOS-Decoder/IDE board at github
https://github.com/agranlund/STBlitter_RevA
But this is realized inside the CPLD

For my H5 STX build, I am using pperas IDE solution (HW and GAL)
This one https://atari.8bitchip.info/aidesch.htm

My experience is limited, so I am not sure what to add and what to change...

reason: I like to be able to add a Lightning ST, mainly for USB. But this comes with own IDE and I think it would be good to allow co-existence...

regards
Michael

[frank.lukas]

... ask Alanh, his MonSTer has two IDE ports because of the address location of the second port.

[rubber_jonnie]

Yes, the monster did have 2 IDE ports. AlanH is definitely the man for that.

[LarryL]

Yes, the monster did have 2 IDE ports. AlanH is definitely the man for that.

Ah, cool

Mhm, don’t find a user with that name here

[Steve]

You can find his email address on his website: https://www.atarikit.co.uk/

[frank.lukas]

Milan Atari Clone has also two IDE ports ...

[czietz]

The Lightning ST's IDE interface occupies the Falcon-compatible address range of 0xF0'0000 - 0xF0'003F. The address is also properly decoded. It won't collide with a second IDE interface that uses 0xF0'0040 - 0xF0'007F.

However, the ppera design (afaik!) is not fully decoded. I.e., it is mirrored at 0xF0'0000 - 0xF0'003F and 0xF0'0040 - 0xF0'007F (and possibly even more addresses). That means that you at the very least have to modify the ppera design to take into account address line A6, so that it is able to distinguish between 0xF0'0000 - 0xF0'003F and 0xF0'0040 - 0xF0'007F.

[LarryL]

The Lightning ST's IDE interface occupies the Falcon-compatible address range of 0xF0'0000 - 0xF0'003F. The address is also properly decoded. It won't collide with a second IDE interface that uses 0xF0'0040 - 0xF0'007F.

However, the ppera design (afaik!) is not fully decoded. I.e., it is mirrored at 0xF0'0000 - 0xF0'003F and 0xF0'0040 - 0xF0'007F (and possibly even more addresses). That means that you at the very least have to modify the ppera design to take into account address line A6, so that it is able to distinguish between 0xF0'0000 - 0xF0'003F and 0xF0'0040 - 0xF0'007F.

Great, thanks.
I think I can figure this out now

Will check and report

Cheers
Michael

[LarryL]

Hi,

Indeed, A6 is not decoded, only A23-A14 and A5

The ppera design also decodes TOS2.06 for two TOS Chips.
Since I only use one, I think I can re-use this GAL-Pin for A6

Need to adapt the equations accordingly…
But sounds doable

One question remains:
Ppera is decoding A23-A14
Agranlund only A23-A16

Can A14/15 be ignored?
Then I could re-use these pins for enable/disable of IDE and configuring the IDE address

Cheers
Michael

[LarryL]

Hi,

Changed the GAL equation, fighted WinCupl (won the fight) and created a new Jedec file.
Breadboarded a little bit

IMG_0934.jpeg (632.64 KiB) Viewed 2266 times

Seems to work

Now I have to cut some traces and solder some more bodge wires

Still not sure if I can work without A14 & A15 to reuse these inputs for IDE port selection and enable/disable…
All pins of the GAL20v8 are in use already…