TF 030 upgrade

[MrPix]

@terriblefire has made himself incredibly hard to contact

I'm poking at an '030 upgrade for the Sinclair QL and am looking for outside inspiration/validation. I'm interested in how the TF1260 handles clocks and SDRAM to see if there's any lessons I can apply.

The catch here is that the project hasn't updated in three years, and it was done in Eagle which is pretty much a dead line in EDAs nowadays. I have had a nightmare time trying to view the files on my ARM Mac.

@terriblefire, would you be interested in converting the files to PDFs or kicad something? Anything?

I know it's an ask and you have people coming at you from everywhere. I'm trying to do something in a very underserved community. Can you help?

Please?

MrPix

[terriblefire]

It should just load straight into the latest kicad. Either the TF1230 or TF330.

keep in mind the TF license is "no derivatives"

[MrPix]

I 1000% respect the license. I have no intention of cut'n'pasting anything. My own work will be released under the CERN OHL-S V2 license.

I have reached a point with my project were everything sorta works sorta well enough, but I learned as I went a few years ago. Now I know a bit more and am revisiting it for possible release. I think it would just be really healthy for the project to look at a couple of other solutions and see if a different approach might be better. The TF1260 is interesting because it's a 'minimal working system' with a stated goal of being lightweight with core functionality and no bells and whistles.

What I have now is:
68030@40
765-compatible floppy controller DD/HD/ED
ATF1508 QFP100 CPLD providing logic for:
Address decode
8MB (2x 4Mx16 PSRAM)
2MB (2Mx8) flash (copies into fast RAM on boot)
parallel port
RTC, battery backed

Equations in WinCUPL. Will likely move to GW1N-9 FPGA and Verilog.

The main thing I'm looking to improve on is to go from PSRAM to SDRAM. The PSRAM is quite complex to use on a 40-50 MHz 030 because the timing gets quite marginal. First accesses take 60 or 70nS, but subsequent accesses to incremental addresses can be ready in 25nS, up to four consecutive reads. At 40 MHz, a cycle is exactly 25 nS so....

[terriblefire]

For the SDRAM code look here

https://github.com/terriblefire/tf1230/ ... tl/sdram.v

The code i have for the 060 stuff is almost identical.

[MrPix]

Thank you kindly, Sir McSir!