Hi,
For my own needs, I have to study more deeply the ISA of our favorites CPUs using the Programming Reference Manual, and I felt the need to organise all those data.
I choose a simple format (Tabulation Separated Values) that you may import into office software (Excel, Calc, Google sheet, whatever), in order to be processable via scripting.
This is an ongoing work (I have to study the coprocessor instruction set and the specific mnemonics of the FPU and various MMUs), but all the integer and privileged instruction are ok-ish. Also, I found interesting that most instruction would be better represented with one hexa digit followed by 4 octal digits, exceptions being notably Bcc where full hexa is more appropriate.
https://github.com/sporniket/isa68k-database
By chance, this will be of help to others. Also I am aware that official documentation may have errors, so I gladly welcome any correction proposal :)
My database of the 68k Instruction Set Architecture
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sporniket
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mrbombermillzy
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Re: My database of the 68k Instruction Set Architecture
Thats a great start there David. :)
So, it seems you are (or will be) writing a compiler/assembler of some sort? (Going by your own admission as the main reason for doing this).
So, it seems you are (or will be) writing a compiler/assembler of some sort? (Going by your own admission as the main reason for doing this).
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sporniket
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Re: My database of the 68k Instruction Set Architecture
Writing a devpac-ish assembler is one of the goal, but having a single instruction compiler would be a great achievement by itself, and anyway a milestone for such a project. The twist being that the compiler engine would use the database (or more likely a byproduct, optimised for usage), and thus have reference implementations in several languages (compiled ones like java, scripts like python, typescript or pure javascript, and low level languages like assembly 68k) (did I say that this is one of those pharaonic projects)
Also, this is a groundwork to implement a core in HDL ; this work was triggered also after reading the methodology presented in the book "Microprocessor Design using Verilog HDL" by Monte Dalrymple (I will use Amaranth instead of Verilog). Honestly that methodology seems more suited for older 8bits CPU, that are simpler. And this is an even more pharaonic project (given that I target 68030 with full MMU implementation ha ha, yes I have big dreams).
So for now such grand plans are just vaporware, and right here and now, there already is that bunch of data that I have organised "a little".
Also, this is a groundwork to implement a core in HDL ; this work was triggered also after reading the methodology presented in the book "Microprocessor Design using Verilog HDL" by Monte Dalrymple (I will use Amaranth instead of Verilog). Honestly that methodology seems more suited for older 8bits CPU, that are simpler. And this is an even more pharaonic project (given that I target 68030 with full MMU implementation ha ha, yes I have big dreams).
So for now such grand plans are just vaporware, and right here and now, there already is that bunch of data that I have organised "a little".
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mrbombermillzy
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Re: My database of the 68k Instruction Set Architecture
Great plans! :)
Absolutely nothing wrong with thinking big.
Funnily enough, Im not sure that you are aware, I am working along similar lines myself (at the formulating period of creating a game creation based high level language compiler with several mainly 68xxx targets).
However, my implementation differs somewhat and is more of a by product from the process of getting my PC game onto other (non x86) machines.
Keep us all posted. This sounds very interesting.
Absolutely nothing wrong with thinking big.
Funnily enough, Im not sure that you are aware, I am working along similar lines myself (at the formulating period of creating a game creation based high level language compiler with several mainly 68xxx targets).
However, my implementation differs somewhat and is more of a by product from the process of getting my PC game onto other (non x86) machines.
Keep us all posted. This sounds very interesting.
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chronicthehedgehog
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Re: My database of the 68k Instruction Set Architecture
Good luck!. Amaranth sounds really interesting - I wished I'd known about it a few years ago.
I gave up on FPGA (using sysverilog) after about 6 months of trying to stop a double read on the FIFO I'd implemented (as part of some Raspi to CMODS7 to ZX Spectrum hardware I was trying to develop which would have allowed multiple USB devices to be interfaced to the Speccy).
Probably trivial to someone with a couple years experience but I just couldn't get to grips with timing constraints especially across multiple clock domains. This might have avoided all the pain :-)
I gave up on FPGA (using sysverilog) after about 6 months of trying to stop a double read on the FIFO I'd implemented (as part of some Raspi to CMODS7 to ZX Spectrum hardware I was trying to develop which would have allowed multiple USB devices to be interfaced to the Speccy).
Probably trivial to someone with a couple years experience but I just couldn't get to grips with timing constraints especially across multiple clock domains. This might have avoided all the pain :-)
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sporniket
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Re: My database of the 68k Instruction Set Architecture
Interesting @mrbombermillzy, I knew only about your research to enhance the display.
@chronicthehedgehog Amaranth is quite nice, compared to VHDL and verilog, especially as it aims to helps beginners like me to avoid basic mistakes. There are complimentary frameworks for writing System-On-Chips that is about to comes, as well as an enriched library of basic modules, I expect that will help a lot.
For now, the only concrete achievement with HDL has been the implementation of the TMDS encoding to display something on a HDMI screen (see viewtopic.php?p=105679#p105679 ), and building my own system to write tests using formal verification.
Progress is very slow, because I have a squad of truckloads of projects, and also during winter motivation and energy was even more low (and I enjoyed a lot Zelda Tears of the Kingdom...)
@chronicthehedgehog Amaranth is quite nice, compared to VHDL and verilog, especially as it aims to helps beginners like me to avoid basic mistakes. There are complimentary frameworks for writing System-On-Chips that is about to comes, as well as an enriched library of basic modules, I expect that will help a lot.
For now, the only concrete achievement with HDL has been the implementation of the TMDS encoding to display something on a HDMI screen (see viewtopic.php?p=105679#p105679 ), and building my own system to write tests using formal verification.
Progress is very slow, because I have a squad of truckloads of projects, and also during winter motivation and energy was even more low (and I enjoyed a lot Zelda Tears of the Kingdom...)
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chronicthehedgehog
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Re: My database of the 68k Instruction Set Architecture
I blame my motivation problems on covid. I had it twice and my head feels like concrete these days :Dsporniket wrote: 04 Apr 2024 22:20 Progress is very slow, because I have a squad of truckloads of projects, and also during winter motivation and energy was even more low (and I enjoyed a lot Zelda Tears of the Kingdom...)
I've just bought some 5-HTP serotonin supplements. Hopefully that will help things :D
It's always good to catch up on some game playing though. I find it hard to put time aside for big games. My wife bought Zelda so I'd like to give that a go. I've also yet to start Metroid Prime Remastered - the GameCube version was probably my favourite game of all time.
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sporniket
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Re: My database of the 68k Instruction Set Architecture
That's tough, I wish you the best to recover fully.
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