Since a week, I'm working on my own 68030 / 32MHz / 16MB TT-RAM expansion based on the amazing DFB1 project.
The idea is to have into my Falcon 030 a little expansion close to what the Falcon was able to be, 30 years ago.
I would like to thanks again D Henderson for his great project that allows to save a lot of time and test (CPLD).
This topic, because I may have some questions around the original DFB1 project related to my work in progess.
- Why the CPU decoupling capacitors have different values than 100nF on the schematic?
- Why the CPU jumpers to disable the MMU and CPU Cache are closed and linked to VCC?
It looks to be forced to enable, while I have expected to find them open and "linked" to GND.
Thank you!
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