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Blitter on H5 Test

General discussions or ideas about hardware.
ijor
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Blitter on H5 Test

Post by ijor »

This is a small test program. I need somebody to run this test on an H5 with Blitter, and ideally with TOS 1.02. Other TOS versions are also useful, but, please, I would like at least one test with TOS 1.02.

The program benchmarks TOS blitting operations, in a very similar way as Gembench does. But this test counts system cycles instead of MFP interrupts. Then the result, at least in theory and if I didn't make any mistake, should be exact and identical in any computer with the same TOS version. Obviously this won't work correctly with any kind of booster.

Testing on an STE could also be interesting, but please not on MSTE because the MSTE has a slightly different Blitter timing.

And H5 is not strictly required, it could be a standard ST (or STFM or MegaST) as long as the pull-ups on the DMA control signals (BR,BG & BGACK) were upgraded. A factory ST with the original 4.7K weaker pull-ups might produce different results. And of course that Blitter is required.

Use medium resolution with Blitter enabled at the desktop, and please post the results.
Again, not on MSTE, not on a computer with an active booster or accelerator, not when using EMUTOS (standard TOS is required).

Thanks
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http://github.com/ijor/fx68k 68000 cycle exact FPGA core
FX CAST Cycle Accurate Atari ST core
http://pasti.fxatari.com
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exxos
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Re: Blitter on H5 Test

Post by exxos »

104 on a H5C1. MM9092V blitter.

IMG_0338.JPG


102 on a H5C1. MM9092V blitter.

IMG_0339.JPG
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ijor
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Re: Blitter on H5 Test

Post by ijor »

exxos wrote: 13 Dec 2022 14:21 104 on a H5C1. MM9092V blitter.
...
102 on a H5C1. MM9092V blitter.
...
Thanks Exxos. Interesting, I wasn't expecting this result on the H5. Seems the H5, at least in this case, has the slower ST timing in comparison with the STE.

Could you confirm exactly which pull-up value you have on the CPU BGACK signal? I though the H5 uses the same stronger pull-ups as the STE. But now, after seeing these results, I checked the H5 schematics again, and I see that the pull-up on this signal is 2K2. While on the STE schematics is 1K2 (and 4K7 on the ST).

I'm not saying that there is anything wrong with the 2K2 value. Arguably it might be better in terms of producing the same timing as the original ST. Just that I expected 1K2 as in the STE.
http://github.com/ijor/fx68k 68000 cycle exact FPGA core
FX CAST Cycle Accurate Atari ST core
http://pasti.fxatari.com
ijor
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Re: Blitter on H5 Test

Post by ijor »

Anybody else? Now, after Exxos post, I would like to see the result on a standard STE and also on a standard STFM (or MegaST). Also another H5 might be useful as well.

Thanks!
http://github.com/ijor/fx68k 68000 cycle exact FPGA core
FX CAST Cycle Accurate Atari ST core
http://pasti.fxatari.com
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Re: Blitter on H5 Test

Post by exxos »

ijor wrote: 13 Dec 2022 19:44 Could you confirm exactly which pull-up value you have on the CPU BGACK signal? I though the H5 uses the same stronger pull-ups as the STE. But now, after seeing these results, I checked the H5 schematics again, and I see that the pull-up on this signal is 2K2. While on the STE schematics is 1K2 (and 4K7 on the ST).

I'm not saying that there is anything wrong with the 2K2 value. Arguably it might be better in terms of producing the same timing as the original ST. Just that I expected 1K2 as in the STE.
It's 2.2K. I can soon slap a 1K in there and test again..
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sporniket
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Re: Blitter on H5 Test

Post by sporniket »

ijor wrote: 13 Dec 2022 19:46 Anybody else? Now, after Exxos post, I would like to see the result on a standard STE and also on a standard STFM (or MegaST). Also another H5 might be useful as well.

Thanks!
I'll try on my STe by the end of the year. (edit : hopefully sooner )
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exxos
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Re: Blitter on H5 Test

Post by exxos »

@ijor

IMG_0339.JPG


Should have used 2.2K I guess :lol: But will doublecheck that as well anyway...

EDIT:

1K is the same as the 680R test.
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EvilFranky
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Re: Blitter on H5 Test

Post by EvilFranky »

Dug out my STE quickly.

TOS 1.62
4MB RAM
Separate Blitter

IMG_20221213_221316.jpg
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ijor
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Re: Blitter on H5 Test

Post by ijor »

exxos wrote: 13 Dec 2022 20:06 Should have used 2.2K I guess :lol: But will doublecheck that as well anyway...
EDIT:
1K is the same as the 680R test.
Thanks. That confirms that the weaker pull-up produces a delay. See the extra 4 cycles on tests 4-6. Again, the delay would only be significant for some blitting operations and only for code running from Rom.
EvilFranky wrote: 13 Dec 2022 22:33 Dug out my STE quickly.
TOS 1.62
Thanks a lot! See how these results on an STE match the ones on Exxos test on the H5 using TOS 1.04 except, again, 4 extra cycles on tests 4-6. Seems all TOS versions from 1.04 to 2.06 share the same Blitter code section, or at least is similar enough to produce exactly the same timing with these tests. TOS 1.02 is rather different.

Thanks again to both.
http://github.com/ijor/fx68k 68000 cycle exact FPGA core
FX CAST Cycle Accurate Atari ST core
http://pasti.fxatari.com
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exxos
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Re: Blitter on H5 Test

Post by exxos »

TOS104 on a H5C1. 1K and 2.2K tests.

104.jpg


TOS206 on a H5C1. 1K and 2.2K tests.

206.jpg

I re-posted 102 here edited to align with the above tests.

TOS102 on a H5C1. 1K and 2.2K tests.

102.jpg
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