JTAG boundary scan

[foft]

I've been working with FPGA boards for a few years now, but never tried a boundary scan. Mostly I could get by on my own boards using signaltap of making custom cores to toggle pins.

I'm now playing with some boards using Xilinx CPLDs, such as the DFB1, the TF1260 and the CT63. I was wondering if anyone tried setting up boundary scan on this. Also the 68060 seems to have a JTAG so presumably I could also do it with that if I pop it on the chain (the BSDL is in the manual, also it has a debug mode...).

I'm guessing you can write code to say turn in pin 1 on device A, check no other pins on device A go high, check device B sees it etc. Or something like that. Though wasn't sure what tooling there is.

This looks kind of neat: https://github.com/colinoflynn/pyjtagbs. Though the docs just say TODO!

[UnderTheRain]

Yes you can toggle I/o on any device connected in series it can get slow though on long chains. Commercial apps out there are very mature with loads of options operating in real time but they come with a hefty price tag even at the bottom end. Most people think JTAG is a programming interface it's a test interface that just so happens also let's you program. I was going to dabble with it last year for work but we don't really need it (we program a lot with JTAG but customers aren't interested in JTAG for test we used bespoke test rigs mostly they're cheap) so I thought it best not to drop a couple of grand on the kit just for me to tinker with. Programmers are cheap I think the very very lowest test interface I found was £600-800 I think

[foft]

I bought myself a 'J-Link' from ali express (presumably a clone) back when I posted about this in December.

I finally tested it last week with the python boundary scan library I linked! The library seems to work well under linux. I can easily read all fpga pins in passive mode without perturbing the function. In active mode I can also set pin states.

Going to be useful...