[Video] Demonstrating the final 16MHz/AltRAM booster prototype

[Badwolf]

I think I've spent enough time on this now. Drawing a line under initial development of the hack-16MHz ST booster.

Here's a demo.



Next step in this project will be correcting the board layout to avoid the tower of terror on display here and then it can go open source.

Hopefully a verilog whizkid can get the blitter working properly for us then. :-)

BW

[Steve]

Love it! AltRAM is amazing! And wtf did XaAES developers think those window borders were suitable for low/medium res displays. One day I'd really like to get AltRAM for my regular ST's.

[Badwolf]

Love it! AltRAM is amazing! And wtf did XaAES developers think those window borders were suitable for low/medium res displays. One day I'd really like to get AltRAM for my regular ST's.

I can't 100% promise I've set up XaAES correctly. I normally use it in ST High, obvs. :)

BW

[Badwolf]

Very close to putting in the order for the next revision (with hopefully correct pin pitch now!).

Screenshot 2022-03-11 at 23.47.15.png

This has actually managed to squeeze everything into two layer, but we'll see what the four layer prices are like as I think it'll help at these speeds (memory runs at 66MHz).

BW

[sporniket]

Impressive work.

The downside of no blitter for me as a game developer, is that I would have to deal with preshifting and blitting by hand, instead of just telling the blitter to do that for me.

Hopefully a verilog whizkid can get the blitter working properly for us then. :-)

Too bad, I selected vhdl as my hdl language of choice for the time being. Anyway I'm not a whizkid either :D

[Badwolf]

Impressive work.

Many thanks!

The downside of no blitter for me as a game developer, is that I would have to deal with preshifting and blitting by hand, instead of just telling the blitter to do that for me.

The blitter can still work in ST-RAM. The problem its the GEM desktop doesn't know that. I need to have a nose at BLITFIX from Anders.

Of course it *should* work, and I have a version of the firmware that *almost* works, but MiNT won't work with that firmware (oddly).

With a bit of a better SDRAM driver or a better top level verlilog design, I reckon it can be made to work and be MiNT compatible.

Too bad, I selected vhdl as my hdl language of choice for the time being. Anyway I'm not a whizkid either :D

I'll put you down as working on the blitter compatibility then! ;)

BW

[Badwolf]

Hi @JezC, I've replied here to keep that other topic for DFB1.

Currently stuck at an airport near Shenzen and has been for a week!

Boo! We need more videos...please!

It's moved! Departed the airport, I'm told.

I might have to re-watch the existing videos as IIRC the problem was that the socket on the top wasn't the correct width...so maybe it would still be an option for something like the H4 or H5 where it could be fitted in one of the expansion sockets & never need to have a socket fitted on the top?

Yeah, I ballsed up my footprint. The new one has, I believe the correct footprint and I managed just about to squeeze it all on. I was naughty and went for a two layer board which might be asking for trouble. It'll fit a lot better on a four.

I was going to repurpose this one as AltRAM only and send it to Exxos to have a play with, but he's now got a much better AltRAM board working and, to tell the truth, I'll probably have to dismantle this one for the CPLD!

I've been having terrible trouble sourcing the CPLDs.

This uses a 10ns XC95144XL in a QFP100 footprint. I can't find any!

I've had pay almost twice the price for the dwindling stocks of 7ns ones. That might actually solve one of my problems (blitter not working) as I think that was likely propagation time related, but it will mean I'm developing on a different chip to the target.

It's all very annoying as I've another project in the pipeline that wants to use this CPLD too. They're £8 a pop normally: right in the sweet spot.

BW

[JezC]

@Badwolf Hoping you get chance to work on this new revision soon - I see what you mean about the 100 pin 10ns CPLDs...worse availability than hen's teeth!

I'll try and put together a comprehensive BOM for one (unless you've collated the info already?)...if only to check I've not missed anything essential ;)

I'll either edit & add at the end of this post if I get it done later today (looking unlikely so far - boo!) or add it as a new post at some point tomorrow.

Did you try it with the full 66MHz Osc? I do have a 16MHz 68000 (or two) here so I'm hoping they (a) work and (b) will overclock very slightly... :roll:

[Badwolf]

@Badwolf Hoping you get chance to work on this new revision soon - I see what you mean about the 100 pin 10ns CPLDs...worse availability than hen's teeth!

I'll try and put together a comprehensive BOM for one (unless you've collated the info already?)...if only to check I've not missed anything essential ;)

I'll either edit & add at the end of this post if I get it done later today (looking unlikely so far - boo!) or add it as a new post at some point tomorrow.

Did you try it with the full 66MHz Osc? I do have a 16MHz 68000 (or two) here so I'm hoping they (a) work and (b) will overclock very slightly... :roll:

In terms of BOM, no, sorry, I haven't. I can put the Kicad files up on GitHub to kick things off, but last I time I did that a couple of guys orderd boards before I'd written the firmware :lol:

The variable oscillator I had hooked up in the last video was running at (just over) 66MHz, which is why the integer division was actually a bit more than 200%, so that has been tested. Of course a slightly slower oscillator will work. A 33 and a divide by two would probably be the minimum else AltRAM would end up slower than STRAM, though.

BW

[Badwolf]

Rev 2 lives!



BW