TF4060 Revision 1 Design Complete

[terriblefire]

I finally found some time to get this done.

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5 of these are off to the board house. I also found time to build a Jenkins server to produce the gerbers, cam files, netlists, ucf/pcf files and build the firmware automatically in one go.

Specs...

1. 68060 CPU (Socket is completely 3.3V) at up to 100Mhz.
2. Up to 256Mb of SDRAM organised as 128Mb of CPU RAM (@0x08000000) + 128Mb of Autoconfig RAM.
3. 1 x Buffered IDE interface (ehide.device or similar).
4. Supports A3000 DMA.
5. Supports DMA from a ZIII Card into Its fastram. (i.e. can boot from a ZIII Scsi card).
6. Couple of non-switched fan headers.
7. 26 Pin Pi-Hat capable of programming of both BUS CPLD and RAM FPGA. Potentially over wifi with a Pi 2 Zero W (powered from the TF4060).

The Pi Hat has Quad SPI wired up to the FPGA and an extra chip select line for "things" down the line. I know some pedant will say its not technically a pi hat because we dont have an ID SPI rom. You are correct.

The only thing I have not got nailed yet is the software frequency change. I need to fix some bugs in archane-pnr for that.

[Danoo]

Excellent news, this is the card I have been waiting for, happy to see that it is off to the board house. :D Wow how do you find the time to progress all these great projects, your other hobbies, work and family, just amazing :o . Many thanks once again to the TF production company :D

[terriblefire]

Excellent news, this is the card I have been waiting for, happy to see that it is off to the board house. :D Wow how do you find the time to progress all these great projects, your other hobbies, work and family, just amazing :o . Many thanks once again to the TF production company :D

TBH i've been sitting on this more or less since i moved house. It was pretty much ready then. The final touches were to fix issues in fomu-flash with the global unlock register and work out how to make the CPLD and FPGA flashable from one header.

In terms of software. I'd like a linux distro setup to create a wifi in host mode. Then when you join the network you can just drop a zip file on a web page and it will flash the card.

[GadgetUK164]

Wow, that's a nice evolution from the proto =O

[sporniket]

That, among all the cool stuff described :

7. 26 Pin Pi-Hat capable of programming of both BUS CPLD and RAM FPGA. Potentially over wifi with a Pi 2 Zero W (powered from the TF4060).

In terms of software. I'd like a linux distro setup to create a wifi in host mode. Then when you join the network you can just drop a zip file on a web page and it will flash the card.

Hat off. An almost foolproof way of updating the update the firmware.

[pipper]

Sir, I sincerely applaud you for your tenacity!

Really looking forward to some day put one of it into my A3000!
I'm especially happy to hear that DMA is fully supported!

:dualthumbup: :thanksyellow: :cheers:

[SnoopDOS]

Excellent news!

[matt020]

2. Up to 256Mb of SDRAM organised as 128Mb of CPU RAM (@0x08000000) + 128Mb of Autoconfig RAM.

Is this transparent to the end user and 256mb is available on every boot, or will the user have to use addmem (or something similar) for that additional 128mb to be available? Cheers and thank you.

[terriblefire]

2. Up to 256Mb of SDRAM organised as 128Mb of CPU RAM (@0x08000000) + 128Mb of Autoconfig RAM.

Is this transparent to the end user and 256mb is available on every boot, or will the user have to use addmem (or something similar) for that additional 128mb to be available? Cheers and thank you.

It should be transparent on OS3.1+, on OS3.0 you'll only get 128Mb same as the TF1260. You could in theory put 2 lots of 64Mb on there too. But why would you?

[alexh]

Looks great. Thanks for all the hard work.

Given the "global chip crisis", are there long lead times on the CPLD & FPGA used here?

Do you think we will see the TF4060 available from our TF builders this year?