Hopefully, someone (or two) will know the answers to the following, which would be a start:
> CPU(s) used in the project?
> CPU(s) speed? (Also, if 030> any 'burst' access and to any fast (i.e. only acessible by CPU) RAM possible?)
> System bus Speed?
> Any unusual wait states/bus arb. for the above? (i.e. any extra cycles added to any access for any reason thats notably different from the standard STs?/ DMA cycle allocations, etc.)
> Shifter operational data RW width/ shift buffer size?
> Is the Phoenix shifter Video Address Pointer or Video Count Position Register switchable with different granularity from the regular ST/TT? (i.e. VBL/HBL/pixel perfect precision).
If anyone can think of any other relevant questions that I have missed, from a software facing perspective, please chip in.


