How to delay one signal of tens of nanoseconds ?

[sporniket]

Hello,

A little bit of context : for my project to replace the ACIAs, I assessed that I needed to use the Enable signal from the 68000 to switch on/off the level translator. And that the switch off should happen between 10ns and 50ns after Enable goes low, according to the MC6850 datasheet.

So I am vaguely remembering that a way to get this delay is to use series of "NOT" gates to accumulate the propagation delays of those gates and obtains the result. I thus plan to use this one (an hex shmitt-triggered inverter) https://www.mouser.fr/ProductDetail/STM ... 2BiQ%3D%3D . I choosed the Schmitt triggered instead of a classic inverter for the histeresys.

and so I have 2 questions :

• Is it the appropriate way to get such delay ?
• The datasheet hints that the propagation delay is dependent to the capacitance of the trace, with 2 datapoints at 15pF (typ. 5.5 ns) and 50pF (typ. 7ns). My traces will be short, especially where I feed one gate output into the input of the next one. Should I plan to add a capacitance (say around 20pF) on each chained output to be sure of the actual delay ?

(I have no oscilloscope and it is out of budget for me, otherwise I could find out the answer to question 2 myself)

[PaulJ]

Out of curiosity why are you replacing 6850's and if so with what? Just something to see if you can do it or you have a specific purpose? :coffee:

[sporniket]

Out of curiosity why are you replacing 6850's and if so with what? Just something to see if you can do it or you have a specific purpose? :coffee:

I want to replace both 6850s with a single ESP32 to connect bluetooth devices (keyboards, mices, game controller and bluetooth midi) instead of the IKBD (and eventually have a bluetooth IKBD as well, but the later is not a priority for me).

The hardware delay is because : I found out that the latency of GPIO interrupt is too high (2 us), even with a workaround that someone has found (50ns). The workaround is fine for reading the bus, but when writing to the bus, the timing constraint to stop driving the bus at most 50ns after E goes low cannot be done by the firmware. Thus I realized that using a delayed E to drive the enable pin of the level translator should do the trick.

[exxos]

Use a 100MHz clock to add 10ns delays.

Use a couple of slow inverters in series.

Use a RC delay.

[cmorley]

If interfacing though a PLD (or CPLD) you can route through a spare pin to get extra delay. e.g. an ATF22V10 pinnode is ~10ns IIRC