CPU booster int-div + blitter speeds

[exxos]

I have been puzzling over something today.. Basically what my boosters do is when something like the blitter has control of the bus, the CPU runs at 8 MHz. This in itself does not really make sense, because, the CPU should be able to run that 32 MHz while something else control the bus. But in reality, for some reason this does not work..

What I think is happening is, because some other bus master will issue DTACK, when it releases the bus, DTACK is likely still low for a short while, But because the CPU is running a 32 MHz it actually reads DTACK and latches bad data on the bus.

Though what I have wired up now, is that there is a exception to the 32 MHz rule, that if /DTACK is high while /AS is high and /BGACK is low, then the CPU is allowed to run at 32 MHz. What happens then is the CPU then switches to 8 MHz when /DTACK goes low. So basically then the CPU will not pick up /DTACK until a little later. This actually works..

Problem is, with GB6, it wasn't designed for multiple bus operations like this. So I wonder if anyone could write a test routine to see if this new booster mod does anything or not.

It would need basically, a long division doing, at the same time as some blitter operation is being done. I am not even sure if this would even work code wise ?

That idea being that, the CPU can run the long division faster while the blitter has control of the bus.. With the classic booster design, the int-div would run at 8 MHz in this situation. But with the new test circuit, the CPU would run at 32mhz during blitter operation. So the int-div would actually complete faster.

Obviously I have absolutely no way of testing this, or no way of knowing if it can even be programmed this way......

[rpineau]

The thing is, as the 68000 has no cache it doesn't run any instruction when it's not bus master.
When there is a bus request, it finishes its cycle and relinquish the bus and wait... doing nothing ... until it can get the bus back.
So running it at 32 MHz when it's not bus master will not give you anything as it will need to switch back to 8MHz when the bus is released to fetch the next instruction from ROM or RAM.
So in you example of the long division, the CPU will not give the bus to the Blitter while doing the division but AFTER it's done with the division.
Rodolphe