Reverse engineer gate logic of the YM2149

[Gunstick]

Hi

while I work on my presentation on ST chiptunes, there are some remaining questions to be solved. Those were mainly raised by Ben (OVR) who works on the sc68 emulator.
Well, what about decapping the chip and watching the silicon?
Some twitter later:

there is some work done on the AY:
http://privatfrickler.de/blick-auf-den- ... ay-3-8910/
Even with indicating which logic part is where.
Now need to get some people to translate the silicon photos into logic gates/transistors.
Keep in mind that the photo is from an AY, which has 16 steps on the envelope, whereas the YM has 32 steps. Mystery: how do those 32 steps stand in relation to the 16 steps of the volume registers?
From this site https://bulba.untergrund.net/elect_e.htm I got some pointers to google stuff
russian english translation:
https://translate.google.com/translate? ... edit-text=

One question I'm asking myself, how is it that when a channel is disabled in the mixer that setting that channel's volume effectively produces a "pop" sound in the output. It's that characteristic which makes digisound possible. But why does the chip do that?

Georges

[exxos]

Interesting project ! I have no idea that stuff though :(

[keli]

One question I'm asking myself, how is it that when a channel is disabled in the mixer that setting that channel's volume effectively produces a "pop" sound in the output. It's that characteristic which makes digisound possible. But why does the chip do that?

I always imagined it's because when a channel is inactive its output is wired high instead of low. It's not changing so it's still silent, but when changing the volume, the voltage output will change accordingly, causing said "pop".

[keli]

I case someone is interested, I found this VHDL implementation of the ym2149: http://www.cpcwiki.eu/index.php/Ym2149

[Gunstick]

can someone translate this VHDL to C or ASM or any other language I understand?

chan_amp := chan_vol(3 downto 0) & '1';

[exxos]

can someone translate this VHDL to C or ASM or any other language I understand?

chan_amp := chan_vol(3 downto 0) & '1';

I have seen (3 downto 0) etc in my circuit when it compiles, it just means the data width 3..2..1..0... (3 down to 0). No idea what the &1 is on the end though. Maybe just adds one to what ever comes so 0 becomes 1, 1 becomes 2 , 2 becomes 3. Making the data width 3..2..1..

[keli]

The & operator in VHDL is the concatenation operator. So chan_amp becomes bits 3,2,1, and 0 from chan_vol plus one additional 1 bit appended to the end. (5 bits in total, with the last bit set to 1)

This means 0 becomes 1, 1 becomes 3, 2 becomes 5, 3 becomes 7, etc.

Edit: Some more detail. If you look at the surrounding context of that line:

Code: Select all

1:        if (chan_vol(4) = '0') then
2:          if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet
3:            chan_amp := "00000";
4:          else
5:            chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone)
6:          end if;
7:        else
8:          chan_amp := env_vol(4 downto 0);
9:        end if;

The uppermost bit of chan_vol selects whether to use the lower four bits as the actual volume (lines 2-6) or to use the current value of the envelope volume (line 8).
Note that the envelope volume is 5 bits, whereas the channel volume only has 4 bits of resolution. In order to map a "1111" (15) of channel volume to full "11111" (31) in 5 bit resolution, line 5 appends that "1" to the end. That would mean however that a channel volume of zero would become 1 after appending. Therefore there is a special case at line 3 that sets the output volume to "00000" in case the channel volume is zero.