Reading & write to RTC 12887 ?

[exxos]

https://pdfserv.maximintegrated.com/en/ ... 2C887A.pdf

Been sat puzzling over how this chip is actually supposed to work. I have MOT timing selected, but firstly confused over DS. It looks like its just basically a inversion of RW ?

Also I don't get how this multiplexed address / data bus is working. I mean, if I do a read from the chip, what address is it reading from ? Do I do a write to the chip to set the register then do a read and it reads from that address ? Or if I do a write to a address, does it actually write the data somewhere which is already on the bus ? Or is it do 2 reads, first read to select the address register, second to read data ?

I can't honestly make heads or tails of any of it

[rubber_jonnie]

Certainly quite a bit different to a DS1315, which only had data in/out rather than address lines.

[stephen_usher]

Multiplexed, Bidirectional Address/Data Bus. The addresses are presented during
the first portion of the bus cycle and latched into the device by the falling edge of
AS. Write data is latched by the falling edge of DS (Motorola timing) or the rising
edge of R/W (Intel timing). In a read cycle, the device outputs data during the
latter portion of DS (DS and R/W high for Motorola timing, DS low and R/W high for
Intel timing). The read cycle is terminated and the bus returns to a high-
impedance state as DS transitions low in the case of Motorola timing or as DS
transitions high in the case of Intel timing.

It sounds to me to write you put the address on the bus, pulse 'AS' high and then low. Put the data on the bus and then pulse 'DS' high/low (Motorola mode) or pulse 'R/W' (Intel mode).

To read is sounds as if you put the address on the bus, pulse 'AS' and then depending upon whether you're on Intel or Motorola mode, set the 'DS' and 'R/W' lines appropriately and read the bus value, then reset the lines.

[exxos]

It sounds like DS just sets how long to hold the data for, which would be pretty much the same time as AS is held low by the CPU. Though looking at the intel timings, DS is inverse of RW...

INTEL READ
AS LOW
DS LOW
RW HI


INTEL WRITE
AS LOW
DS HI
RW LOW

So in my firmware I just put...

Code: Select all

RTC_CS = ADDR:[FF8964];
RTC_RW = ST_RW;
RTC_AS = CPU_AS;
RTC_DS = !ST_RW;    
RTC_RESET = RESET;

Not sure if that will work, but even so, still confused on how registers are selected for read and write, vs actually writing to a address register etc.

Wonder if there is just a version of this chip which isn't multiplexed, would make life a whole lot easier

[exxos]

I found this PDF https://www.maximintegrated.com/en/app- ... vp/id/1145

Not sure it really helps tho

[exxos]

hmmm, I think "AS" on the RTC is literally address select, and data otherwise... I've been mistaking it for "AS" on the CPU which isn't "AS" on the RTC

EDIT:

yep.

http://www.waveguide.se/?article=ds1685 ... torola-bus

The problem with the DS1685 is that is it not made for the Motorola bus. It's got a multiplexed Intel-like bus. The usual RD, WR and CS signals are there but there is also an ALE signal. The ALE serves as an address strobe input. A falling edge on the ALE causes the DS1685 to latch an 8-bit address from the data lines. Keeping the ALE high while reading and writing changes the data at the selected address.

Then it seems "DS" is just a inversion of "AS".

[stephen_usher]

Then it seems "DS" is just a inversion of "AS".

I'm not sure that's quite the case. It depends upon whether the chip is in Motorola or Intel mode from how I read the documents.

But yes, 'AS' tells the chip to read an address and 'DS' to read/write data, along with 'R/W'.

Oh, and yes, acronym collisions can be a killer!

[exxos]

Its wired for MOT timing. It says DS sets the time it drives the bus. So makes sense when AS is high, its loading the address, so we don't want it to drive data on the bus, so DS is kept low.

So when AS goes high, we basically select data access, and DS sets how long we want the RTC to output data.

Access would have to be done with 2 68000 bus cycles.. but not sure yet how the RTC will behave if it doesn't see CS low the whole time... I'm making the assumption (in my head for the moment) that the address will stay latch even when the RTC is not selected.. it does seem to suggest that in the pdf...

[exxos]

The problem I see is, my RTC board is only wired into the databus.. There would be no way to keep CS low and do both address and data bus cycles in 1 single 68000 cycle .

I think it would be simpler to wire the RTC AD pins to the 68000 address bus, and have a multiplexer chip which can switch out the address bus for the databus. This way it could all be done in a single 68000 cycle, and each RTC address would be mapped into a 68000 register, which may help make software side of things easier. But then I would need a new PCB

EDIT:

Saying that, the Falcon has it wired to the databus it seems.. So it must work with 2x 68000 bus cycles...


EDIT2:

9.jpg (29.83 KiB) Viewed 5231 times

The Falcon CPU must read the address register and dump it on the databus... then read or write to the data register...

[exxos]

6.jpg (57.92 KiB) Viewed 5225 times

So CS going high doesn't clear the selected address I think...

So the 68000 would put the address on the databus, CS = low, DS=low, but can't figure out what RW is supposed to be doing at that point

I mean the first bus cycle would select the register, then read or write data to it on the second bus cycle... but its unclear what RW is supposed to be during the register select cycle

Looking at the intel timings, RW is high in both register select cycles.. so assume thats the way to do it...