H1 SCHEMATIC 20/12/2018

[exxos]

H1.png

Zipped..

H1.zip

This is the current revision of the schematic.

Things to add yet is the 1772 GAL (for AB switch & 16MHz floppy 1.44MB) .

Still not sure what to do about IDE yet.. I may just leave that for another time, main thing is that with a 68000 header now, a IDE prototype board can be plugged into there anyway. So saves a lot of work for now.

The bulk of the work yet , will be adding all the PCB holes, locating everything.. Hopefully I can make a start on that after xmas...

[Icky]

Nice work Exxos :bravo:

Had a first glance for missing pull-ups don't see any so far :)

Nice to see the RW on the Rom Cart port

[PhilC]

Nice work Exxos :bravo:

Had a first glance for missing pull-ups don't see any so far :)

They will be there, hiding in plain site, sarcastically waving, where we can't see them, little b*ggers :lol:

[PaulJ]

Nice work Exxos :bravo:

Had a first glance for missing pull-ups don't see any so far :)

They will be there, hiding in plain site, sarcastically waving, where we can't see them, little b*ggers :lol:

Is eagle capable of printing out a net list? If so that would be helpful in checking the different nets.

[exxos]

Is eagle capable of printing out a net list? If so that would be helpful in checking the different nets.

FILE - EXPORT

[PaulJ]

Is eagle capable of printing out a net list? If so that would be helpful in checking the different nets.

FILE - EXPORT

Could you post a zip of the net list for the board? It would make verifying the nets more logical. Understand if you don't want to.

[exxos]

Could you post a zip of the net list for the board? It would make verifying the nets more logical. Understand if you don't want to.

Fine by me... Not sure what use it really is though.

1.txt

[PaulJ]

Could you post a zip of the net list for the board? It would make verifying the nets more logical. Understand if you don't want to.

Fine by me... Not sure what use it really is though.



1.txt

I think if one looks at the net list it would be easier to spot connections that shouldn't exist like the serial data in connected to the 1772 data in. When a lot of thing are connected via label is easy to miss connects.