Cycle exact FPGA recreation

[troed]

Ijor's analysis work has paid off. It runs Closure

http://www.atari-forum.com/viewtopic.ph ... 18#p355918

[exxos]

Whats that for exactly a new mist core or something ?

[troed]

Whats that for exactly a new mist core or something ?

Well MiSTer*, but it means there's finally cycle exact VHDL implementations.

*) https://github.com/MiSTer-devel/Main_MiSTer/wiki

[exxos]

Sweet!

[sandord]

That sounds wonderful!

I'm very curious what this could mean to the future of the STF Remake Project.

[exxos]

I'm very curious what this could mean to the future of the STF Remake Project.

I'm not really sure, because the suska ones were direct replacements for chips, MiST doesn't have a lot of signals as its all internal, so you can't really use these cores (AFAIK) with the stuff I am doing.

In case of the STF, its uses a real CPU, and other chips are locked into 8MHz clock, so even if the cores are not 100% timing wise, it probably won't matter.

[ijor]

I'm very curious what this could mean to the future of the STF Remake Project.

I'm not really sure, because the suska ones were direct replacements for chips, MiST doesn't have a lot of signals as its all internal, so you can't really use these cores (AFAIK) with the stuff I am doing.

The cores weren't specifically designed for MiST or MiSTer. It is possible to use them as a replacement for real chips with some minor modifications. This wasn't tested though.

To be honest, and once you design for FPGA cores, I don't understand why you would want separate FPGA chips. It is much better in almost every sense, and even cheaper, to use a single unified FPGA. But oh, well, this is none of my business.

[exxos]

To be honest, and once you design for FPGA cores, I don't understand why you would want separate FPGA chips. It is much better in almost every sense, and even cheaper, to use a single unified FPGA. But oh, well, this is none of my business.

Because as you know there is already MisT, Firebeee, Suska, we are not wanting to make another "clone". Currently there is no 100% backwards compatibility, that was main aim of project, plus fixes and easier upgrades. Though FPGA is looking unlikely as I don't have time to go into all that anyway.

[MasterOfGizmo]

I actually think there's something in between the MiST and your board. That's a board that fits into the original ST case, has all the connectors a real ST had and is otherwise made of one or more FPGAs. The functionality would be the same as your device but you wouldn't have to rely on slaughtered STs. Maybe that's something for a time when used ST's become rare.

[exxos]

I actually think there's something in between the MiST and your board. That's a board that fits into the original ST case, has all the connectors a real ST had and is otherwise made of one or more FPGAs. The functionality would be the same as your device but you wouldn't have to rely on slaughtered STs. Maybe that's something for a time when used ST's become rare.

we are already looking into this, we had some limited success with the blitter using the suska core. Ultimately we want to replace the chips which are no longer obtainable in a single FPGA. Really we would want them to be as compatible as possible to the originals. But that is pretty much the long-term goal. Of course we don't want to go full FPGA, as we do not want to start recreating the MiST / suska as obviously that already exists