Not sure this is a very good idea. Working fully synchronously with the main ST clock is, of course, good. But if you got rid of the 200 MHz clock, that means that the RPI inteface and processing is asynchronous, and this is not good at all.dad664npc wrote: 07 Jan 2026 08:22 So I rewrote the firmware to use the Atari 8 MHz CPU clock instead of a 200MHz gpio derived clock.
Hmm, why you would need a dedicated signal for RESET? Anyway, seems like you still have some extra GPIO space, or am I missing something?This had the added bonus of freeing up one gpio signal for RESET.
It shouldn't be too difficult to support both latch types. It's not clear to me, at all, how this could affect performance. I could understand if it wouldn't work. But why a different type of latch that doesn't affect the control signals, would affect performance? I checked the repo to see if I could spot something, but seems to be fixed to just one latch type?The current GitHub repo uses this. The firmware for this repo will only work with one latch type though and no matter what I did I just could not get the other latch type to work at the same performance. And that’s where I’m currently at.
I would actually get rid of the latches. I don't think they contribute too much if at all. Mostly they just make the timing more complicated. But, of course, this would require new hardware.
I beg to differ, but I think you got the order wrong. Firmware development should be last. As I said previously, you first need to establish that the PI side and the protocol runs smoothly and reaches full 4MB bandwidth. Then the hardware. And only then the firmware.Until a stable firmware is written no other development in functionality is worth the time.
Not sure I understand why this would be the main performance issue. Can't the PI bit bang the GPIO fast enough to be able to multiplex the interface? Surely ii can bit bang way much faster than 8 MHz?The main inefficiencies come from the 16 bit io transfers for the pistorm protocol. This is limited by the raspberry pi gpio count . So any new solution needs to take that into account.
Anyway, it seems to me that several GPIO pins are wasted. Why in earth would you need 4 dedicated JTAG pins? I realize this is something coming from the original design. But this could be "fixed" in a new hardware version and "automatically" bring you 4 extra GPIO pins.
Well, yes, unfortunately the ST scene is pretty small. But one thing is related to the other. Personally, I would refuse to waste my time helping on such an obsolete design. Working with a modern FPGA would make development far much easier.Comments have been made about the outdated CPLD. Yes, this project would benefit from newer solutions. Also development. Who will do it? The Atari scene is devoid of support.
Why discord? Not sure this is the best way to attract developers or contributors. Why not here or some other Atari forum?If there are any genuine developers out there then reach out in the discord channel.

