Raven060 (kodak80 build)

[kodak80]

This is not at all thought through properly, just thinking out loud :)
But we can steer the logical cartridge address range to an ISA-MEM access with the PMMU.
Would "just" need to avoid that the (isa-space) range isn't colliding with what a graphics card may think belongs to it.
Possibly by A0-A19 being lower than $A0000, and then also some quite high address bit(s) being set to put it out of the way of potential linear framebuffers.

Something like

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ISA      Cart
A0-A15   A0-A15
A16       Rom3/4 select
Ax       Cart select
D0-D7    D8-D15
D8-D15   D0-D7

Ax signals TBD, perhaps at ISA space 8MB or something like that.
(cpu) 0xFA0000 -> (isa) 0x800000
(cpu) 0xFB0000 -> (isa) 0x810000

The card would need some logic, similar to a normal ISA card, to decide if the access is for it. And then also to generate some of the signals for the cartridge port.

I am currently designing a revised Raven ISA cartridge PCB board with a GAL16V8 IC for the coding logic on the board.

I am currently routing A16–A23 and MEMRD from ISA socket to the GAL IC on the new board. This will allow me to update the GAL logic depending on the address space to be used and agreed mechanisms.

here is the logic at the moment:

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/*
   Raven ISA Cartridge Port Decode PAL
   -----------------------------------
   This PAL recreates the Atari ST cartridge ROM3/ROM4 decode
   using ONLY signals available on the Raven ISA bus.

   ISA provides:
     - A0–A23
     - /MEMR (memory read strobe)

   ISA does NOT provide:
     - 68000/68060 AS
     - 68000/68060 RW

   Therefore /MEMR is used as the cycle qualifier.
   /MEMR already implies:
     - valid bus cycle
     - memory space
     - read cycle

   Address ranges decoded:
     ROM4 → 0xFA0000–0xFAFFFF
     ROM3 → 0xFB0000–0xFBFFFF

   Upper address byte:
     FA = 1111 1010₂
     FB = 1111 1011₂
*/

/* ---------- Pin Assignments ---------- */

PIN 1   = MEMR;    /* ISA /MEMR (active low) */
PIN 2   = A16;
PIN 3   = A17;
PIN 4   = A18;
PIN 5   = A19;
PIN 6   = A20;
PIN 7   = A21;
PIN 8   = A22;
PIN 9   = A23;

/* Outputs to Atari cartridge socket */
PIN 18  = ROM4;    /* Active low */
PIN 19  = ROM3;    /* Active low */

/* ---------- Logic Equations ---------- */

/*
   ROM3 = /MEMR & A23..A16 = 11111011₂
   ROM4 = /MEMR & A23..A16 = 11111010₂
*/

ROM3 = !MEMR &  A23 & A22 & A21 & A20 & A19 & !A18 & A17 &  A16;
ROM4 = !MEMR &  A23 & A22 & A21 & A20 & A19 & !A18 & A17 & !A16;

RavenISA_Cart_v1.0.png

Happy to take feedback on things so far. Prototype PCBs ordered as the undecided bits should be in the GAL logic :)

[agranlund]

Very cool!

The address range on the ISA side isn't all that cruicial for Raven and as long as it's 4kb aligned we can pmmu map the cpu side address to whatever you pick on the ISA side.

Perhaps somewhere in the ISA $Exxxxx region would be safer?
More than high enough to avoid where gfxcard LFB lives, and at the same time paranoid enough to avoid $Fxxxxx which some older SVGA cards may have hardcoded for their linear framebuffer (Trident mostly, I belive).

Since you have plenty of spare outputs you could trace out /MEMCS16 and /NOWS as well if you wanted.
Neither are strictly necessary for Raven but if you wanted to use the card in a PC perhaps.
These are open collector active low but I think ATF16V8 does have per-pin .oe in complex mode?

Happy to take feedback on things so far.

I am by no means an expert so I wouldn't really listen to me, and risks are probably zero here anyway, but a few of the traces appear to be hugging each other without really needing to as there's plenty of space for them to spread out a bit more :)

[kodak80]

Very cool!

The address range on the ISA side isn't all that crucial for Raven and as long as it's 4kb aligned we can pmmu map the CPU side address to whatever you pick on the ISA side.

Perhaps somewhere in the ISA $Exxxxx region would be safer?
More than high enough to avoid where gfxcard LFB lives, and at the same time paranoid enough to avoid $Fxxxxx which some older SVGA cards may have hardcoded for their linear framebuffer (Trident mostly, I believe).

Here is my proposed logic:

Code: Select all

/*
   Raven ISA Cartridge Port Decode PAL (E-region mapping)
   ------------------------------------------------------
   This PAL generates Atari ST-style ROM3/ROM4 signals for a
   cartridge port, using ONLY signals available on the Raven ISA bus.

   ISA provides:
     - A0–A23
     - MEMRD (active low memory read strobe)

   The cartridge ROM address space on the CPU side:
     CPU 0xFA0000 → ROM4
     CPU 0xFB0000 → ROM3

   On Raven, the PMMU will map these CPU addresses into an ISA
   window in the E-region:

     ISA 0xE0_0000 → Cart ROM4
     ISA 0xE1_0000 → Cart ROM3

   This PAL decodes the ISA-side addresses:

     ISA 0xE0_0000–0xE0_FFFF → ROM4 (64 KB)
     ISA 0xE1_0000–0xE1_FFFF → ROM3 (64 KB)

   Total window: 128 KB, 4 KB aligned, safely in 0xExxxxx region.
*/

/* ---------- Pin Assignments ---------- */
/* Inputs from ISA connector */

PIN 1   = MEMRD;   /* ISA MEMRD (active low memory read) */
PIN 2   = A16;
PIN 3   = A17;
PIN 4   = A18;
PIN 5   = A19;
PIN 6   = A20;
PIN 7   = A21;
PIN 8   = A22;
PIN 9   = A23;

PIN 20  = VCC;
PIN 10  = GND;

/* Unused pins (available for future features like /MEMCS16, /NOWS) */

PIN 11  = NC11;
PIN 12  = NC12;
PIN 13  = NC13;
PIN 14  = NC14;
PIN 15  = NC15;
PIN 16  = NC16;
PIN 17  = NC17;

/* Outputs to Atari cartridge socket */

PIN 18  = ROM4;    /* Active low chip select for ROM4 */
PIN 19  = ROM3;    /* Active low chip select for ROM3 */

/* ---------- Logic Equations ---------- */

/*
   ISA address breakdown (24-bit):

     A23 A22 A21 A20 A19 A18 A17 A16 A15 ... A0

   Target windows:

     ISA 0xE0_0000 = 1110 0000 0000 0000 0000 0000₂
       A23=1, A22=1, A21=1, A20=0, A19=0, A18=0, A17=0, A16=0

     ISA 0xE1_0000 = 1110 0001 0000 0000 0000 0000₂
       A23=1, A22=1, A21=1, A20=0, A19=0, A18=0, A17=0, A16=1

   We ignore A0–A15 in the PAL; they go directly to the cartridge
   as address lines. The PAL only cares about A16–A23 and MEMRD.

   Decode:

     ROM4 asserted when:
       - MEMRD is low (valid memory read)
       - A23..A17 = 1110000₂
       - A16 = 0

     ROM3 asserted when:
       - MEMRD is low
       - A23..A17 = 1110000₂
       - A16 = 1
*/

ROM4 = !MEMRD
        &  A23 & A22 & A21
        & !A20 & !A19 & !A18 & !A17
        & !A16;

ROM3 = !MEMRD
        &  A23 & A22 & A21
        & !A20 & !A19 & !A18 & !A17
        &  A16;

/* End of file */