Falcon FPGA Core now on MiSTer

[ijor]

Same for FPGA, the gates are not necessarily "simulating" the target hardware on a 1:1 basis, because not enough cells, or no original netlist to base the design on, etc.

That's not true. Most accurate FPGA cores do "simulate" the original hardware pretty close. Mine certainly are. We do follow the original design. Either using original design files, or reverse engineering the hardware (decap). Ideally both. The main reason why it doesn't exactly replicate the original hardware, is because legacy designs don't follow good synchronous design practices.

Regarding not having enough LEs (cells). That might be true for certain later 32-bit platforms. Otherwise that's rarely the problem. Videl e.g, the Falcon video chip (very relevant for this thread that references a Falcon core), has about 2K gates (gates, not transistors). Other Atari custom chips I researched are typically even smaller, sometimes much smaller. You can fit multiple full ST cores instances on an FPGA like the one on the MiSTer.

The main reason that some FPGA cores are based on emulators and not on the hardware is because the author is not familiar with the platform. Many times he doesn't have access to the hardware. Or the author might just find easier and faster to follow a good emulator than researching and reverse engineering the hardware.

[ijor]

Videl e.g, the Falcon video chip (very relevant for this thread that references a Falcon core), has about 2K gates (gates, not transistors).

Small correction just to be accurate. That figure is for actual "gates" only. It doesn't count the Falcon Palette RAM that takes a considerable space in the die. For the purpose of this discussion doesn't matter too much because modern FPGAs have plenty of internal RAM.