Blitter investigations and research from a software perspective

[mrbombermillzy]

Despite the above comments, I tend to not give up easily and try to exhaust all avenues before calling it a day.

With that in mind, I'm going to have to write some test code to answer questions about some specific behaviour from the blitter, unless some kind soul here already knows the answer (and can save me the precious time of writing a test program by explaining whatever it is I have overlooked or maybe confirming my assumptions below). :D

Anyway, I'm currently looking into whether the blitter suffers the same penalty as the 68000 CPU for writes (or in this case blits) to odd addresses.

I have to re-write my code, as I may have overlooked something, but from using my visualisation routines, it seems that if I offset a write to palette index 0 by one byte i.e. to start at $ff8241, or I don't; either way, I get White (colour value 1911/%0111 0111 0111) which is the first colour sent to the palette:

Evenpalblit1.jpg

Oddpalblit1.jpg

However, if the colour data is offset by a byte and the shifter can only accept a full word, so will 'double up' the byte, shouldn't I be seeing magenta (red+blue) on index 0 as with the offset only the (what were the red) bottom 3 bits from the top byte are now residing in the bottom byte of the palette word with them being repeated in the top byte too? (All blits in the pictures are to background/palette 0, with just the first needed for the example).

Seems that possibly the MMU is even aligning the blit..? (Better than a bus error I guess).

[czietz]

Without looking it up (in the schematics at https://www.chzsoft.de/asic-web/) I would assume that the Blitter doesn't even have the LSB of the address implemented. In other words: you can't write an odd source or destination address to the respective registers.

[Cyprian]

yep, there is no A0 (even / odd) address on the 68000 bus. An odd odd address can be reached with LDS / UDS signals which, If I'm not wrong, are not used by the DMA and the BLiTTER.

[ijor]

Anyway, I'm currently looking into whether the blitter suffers the same penalty as the 68000 CPU for writes (or in this case blits) to odd addresses.

As other have commented, Blitter can't perform an access at an odd address. As documented in the official Atari manual, Blitter address registers lack bit 0. The increment registers don't have bit 0 either. All accesses are word oriented. There is no mechanism to access a single byte, not even at an even address.

Relevant manual page:

https://archive.org/details/User_Manual ... 9/mode/2up

[mrbombermillzy]

Thanks for the replies guys. Much appreciated. :)