exxos blog - random goings on

[exxos]

PCBWAY drama continues. Seems I screwed up this time. I sent 34 PLD's for Flashy clock, only they only seem to have 23. So no idea what's happened there as I counted the stuff several times before stuff was sent to them. It doesn't help I seem to be explaining this stuff to 2 or 3 different people all the time.

I confused Trudie PLD thinking it was 5V, but it was the same PLD's as flashy clock, 3.3V. So it explains why I have 50 3.3V PLD's here :roll: I ordered 2 or 3 lots from different places in case 1 lot never turned up. So assumed i just had "left over stock" :roll:

Now they saying I haven't sent 32way header pins, I sent them almost 300 of the buggers. Just told them for the 50th time what orders they were for and sent them images of what I sent in the box.

The IDE headers seem to have gone missing. Its adding more confusion as there are various lengths / pitches of pins across my orders. I remember taking them out of my draw but not sure if I sent them now.

Granted I screwed up a couple times not sending all the parts. But its like half a box of stuff has gone missing. Annoyingly I didn't take images of the last couple of boxes I sent showing the parts :roll:

It's good PCBWAY are checking this stuff. But this has all been ongoing for weeks now. It's all way more effort than it all needs to be. For what I've blown in shipping and taxes sending stuff to China, I could have just got my mate to solder all the header pins on :roll:

[exxos]

Sooooo sick of coughing... :cussing:

Anyway, new ROM decoder "working".

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Though the BERR logic seems to stop the thing from booting up :shrug:

Answers on a postcard...

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"A" is the ROM_CE line, so we know that works. /RW. So on WRITE that will be low. /AS will be low on bus access. "Y" will be low on all those conditions and set BERR low on a tri-state buffer.

So why does it not boot up with IC3 which is controlling BERR ?!

I only checked with my meter as to tired to get the scope out. BERR seems to be high all the time. So can only assume some glitch on power up or something :shrug: No idea.

The BERR logic is kinda pointless anyway as the GLUE will issue BERR anyway. But nothing is ever simple is it :)

[PhilC]

@exxos i'm hoping to get mine built tomorrow, give me a shout if there’s anything I can help with.

[bigbloke]

Though the BERR logic seems to stop the thing from booting up :shrug:

Answers on a postcard...

"A" is the ROM_CE line, so we know that works. /RW. So on WRITE that will be low. /AS will be low on bus access. "Y" will be low on all those conditions and set BERR low on a tri-state buffer.

So why does it not boot up with IC3 which is controlling BERR ?!

I only checked with my meter as to tired to get the scope out. BERR seems to be high all the time. So can only assume some glitch on power up or something :shrug: No idea.

The BERR logic is kinda pointless anyway as the GLUE will issue BERR anyway. But nothing is ever simple is it :)

From the 68000 manual: "The bus error pin also has an effect on processor operation after the processor receives an external reset input. The processor reads the vector table after a reset to determine the address to start program execution. If a bus error occurs while reading the vector table (or at any time before the first instruction is executed), the processor reacts as if a double bus fault has occurred and it halts. Only an external reset will start a halted processor."

I think somehow your circuit may be asserting /BERR at power up just enough to cause this lock up. How strong is the /BERR pull up? Or do you have a glitch occuring in the ROM_CE decoder during a different (non-rom) write cycle (so that it and /AS and /RW are all low for a moment and driving /BERR?

[exxos]

I think somehow your circuit may be asserting /BERR at power up just enough to cause this lock up. How strong is the /BERR pull up? Or do you have a glitch occuring in the ROM_CE decoder during a different (non-rom) write cycle (so that it and /AS and /RW are all low for a moment and driving /BERR?

I think its 2.2k. The BERR is only allowed on ROM access. The block I posted means /AS must be low and RW low in order to issue BERR. Basically a ROM write when the CPU must be running.. Shouldn't happen. So can only assume a glitch on power up. I'll try and get the scope on it tomorrow.

[Badwolf]

...Only an external reset will start a halted processor."

I think somehow your circuit may be asserting /BERR at power up just enough to cause this lock up. How strong is the /BERR pull up? Or do you have a glitch occuring in the ROM_CE decoder during a different (non-rom) write cycle (so that it and /AS and /RW are all low for a moment and driving /BERR?

If it were a power-up glitch then you'd expect a reset, post power-up, to releive the problem.

@exxos: does BERR ever actually toggle low at all? Should happen a few times during boot.



EDIT: that said, the datasheet does say

• To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor;

So hacking a pull-up onto the OE pin might do the trick?


BW

[exxos]

• To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor;

So hacking a pull-up onto the OE pin might do the trick

A good thought. Though I'd assume if the CPU is in reset it shouldn't matter the state of BERR. Everything should be powered up by the time reset goes high. Will try and get the scope out later and see what's going on.

[exxos]

PCB drama continues. Seems I need at least 63 ATF1508 chips but only have 53 :roll: So will get all 34 flashyclocks made up and instead of 50 Trudie, there be about 40. PCBWAY said chips are $50 each, so no thanks.

[exxos]

I would guess BERR isn't supposed to be doing that.

Looks like /AS goes low fine the first time. But on the second /AS pulse low, BERR goes low and keeps pulsing with /AS after that.

RW is high for the first few BERR signals. So with it being a OR function. It should simply not be setting BERR low.. Guess I will have to check the right IC's have been fitted on the PCB or something. :shrug:

IMG_0092.JPG

[exxos]

:WTF:

/RW goes to 2 chips, they are connected.

1.JPG

BUT on the PCB...

2.JPG

I'm getting too old for all this sh*t :roll:


EDIT:

FFS!

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Words cannot describe how much I hate Eagle :pullhair: :headbang:

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