PLD SDRAM controller ?

[terriblefire]

If you think a smaller chip wont do, I can probably just port the TF stuff right over..I think that is what you basically suggested a while back anyway.. I need to do the address decoding in the thing, so thats 23 address lines gone right off the bat.

Inputs:
----------
1 CLK
23 Address lines
2 AS + RW
2 LDS + UDS (either you need to pass them through the CPLD or put buffers in as the SDRAM is 3.3V)

Outputs:
---------
1 CLK
1 CLKE (BTW i tested some rams with CLKE tied high on the TF4060 due to a f*ckup and it worked)
13 Address lines
2 Bank address lines
3 RAS,CAS,WE
1 Chip Select (optional?)
2 LDS,UDS

[exxos]

DTACK...

Though I don't tend to use LDS UDS , might not be relivant with just 1 ram chip anyway..

I could always pass the address bus though some in buffers.. I guess it depends on price of the PLD vs a couple more buffer chips..

[terriblefire]

DTACK...

Ooops yes.

Though I don't tend to use LDS UDS , might not be relivant with just 1 ram chip anyway.

Need to be able to write bytes! (UDS/LDS encode A0). For reads you don't care.

[exxos]

Need to be able to write bytes! (UDS/LDS encode A0). For reads you don't care.

Ah yep. Good point.

[cmorley]

I need to do the address decoding in the thing, so thats 23 address lines gone right off the bat.

You don't necessarily need to route all the address lines through the CPLD. You need the SDRAM address lines to set up the mode but you can externally MUX the address with 74 series buffers and just have two OE from the CPLD & set the CPLD outputs high-Z when the mode is complete. Then you only route in the high address lines as needed for address decoding.

If you want to keep cost down then you need to delete as much as you can from the SDRAM controller or else your CPLD is going to be a £7-15 part & you might as well have used 5v EDO RAM + a £1 PLD.

[Badwolf]

There is the TF sources... officially here..
https://github.com/hologenics
My original SDRAM controller is...
https://github.com/mist-devel/archimede ... /rtl/sdram

Thanks for linking these :dualthumbup:

BW

[exxos]

If you want to keep cost down then you need to delete as much as you can from the SDRAM controller or else your CPLD is going to be a £7-15 part & you might as well have used 5v EDO RAM + a £1 PLD.

It needs to fit in a 68k footprint. So a sdram of like £2 is fine.. Plus some data buffers ., plus whatever pld I can get away with.

I want to keep the full address bus input as I may well add other stuff in at a later date.

[Badwolf]

If you want to keep cost down then you need to delete as much as you can from the SDRAM controller or else your CPLD is going to be a £7-15 part & you might as well have used 5v EDO RAM + a £1 PLD.

It needs to fit in a 68k footprint. So a sdram of like £2 is fine.. Plus some data buffers ., plus whatever pld I can get away with.

I want to keep the full address bus input as I may well add other stuff in at a later date.

The 100-pin version of the XC95144XL would give you 81 IOs -- not enough to buffer the address lines, but enough for everything else with a bit to spare.

It could be made to fit with a bit of creative routeing and decent number of layers, I reckon.

Screenshot 2021-01-17 at 20.11.41.png

Look at all that room on the back for caps! :lol:

They are £8 parts, though.

BW

[exxos]

So it does have the address inputs to the PLD ? would either need to find 5V RAM or use the larger PLD I guess. Though with cost of RAM its probably just going to look like going with the larger PLD.. assuming it would fit in the 68K footprint.. which I am guessing wont ?

@Icky is the creative routing expert these days ;)

[Badwolf]

So it does have the address inputs to the PLD ? would either need to find 5V RAM or use the larger PLD I guess. Though with cost of RAM its probably just going to look like going with the larger PLD.. assuming it would fit in the 68K footprint.. which I am guessing wont ?

@Icky is the creative routing expert these days ;)

Can use the 3.3.

That QFP-100 represents the CPLD, there are two 8-bit buffers for the data lines plus a regulator and RAM. They do just about fit within the 68k footprint. The RAM chip I've put on there is the 16-bit 64MB one I'm using -- overkill on a 68k so should be even more room, TBH. Need to squeeze programming pads/header on there too, though.

I reckon even with all address pins you won't need more than 60 IOs, so I think it'd fit and you'd have ~24 spare. Not *quite* enough to buffer the address too (hence the two 8 bit level shifting buffers), but close and I may have overestimated pin count.

Edit: just thought, the controller would fit in the XC9572XL too -- that has only 72 IOs on the 100 pin version, but still more than enough. £4 chip instead!

BW