H5A Phoenix Platform Edition - A platform for the future

[terriblefire]

You stuck with 24 bit address with a 68k socket. Designing in a processor card bus would allow for full 32 bit and other I/O without additional jumper wires.

Only the CPU can use 32bit address, so 24bit on the sockets is irrelevant,

Indeed. Everything on the Atari is 24 bit address space anyway.

[WiseGreasyBastard]

Only the CPU can use 32bit address, so 24bit on the sockets is irrelevant,

Using the existing hardware that's true.
You could map new hardware into the new space, but who is going to bother making the new hardware?

It was just an idea.

[JezC]

You can do this already with the H4. Remove the cpu and plug in a TF536 like others have done.

Agreed. My question was that if everyone is already going to grab a TF536 and put them in these boards then its probably worth integrating... its not like it would be lots of work.

@terriblefire I'd probably think about starting this as a separate topic or any responses are likely to get 'lost' in the H5 developments.

I'd love an option for an integrated accelerator like that (as I am not confident of my SMT skills ATM)!

[DoG]

Can we add the IRQ from ASCI port pin 10 somewhere on the board? Maybe under the ASCI port perhaps or near the four 68k sockets? Just a single pin would be nice so you don't have to solder a on a leg.

Great for pcb that have IDE and boot from HDD function in TOS.

[terriblefire]

Can we add the IRQ from ASCI port pin 10 somewhere on the board? Maybe under the ASCI port perhaps or near the four 68k sockets? Just a single pin would be nice so you don't have to solder a on a leg.

Great for pcb that have IDE and boot from HDD function in TOS.

I'll second this although i'd like to find a solution like the Amiga one on the TF534/TF536

[exxos]

There are 2 headers with it on already...

[DoG]

There are 2 headers with it on already...

Great.

EDIT: Aah, you mean the internal ASCI port for US and Mega STe port. Of course.

[Icky]

There are 2 headers with it on already...

Great.

EDIT: Aah, you mean the internal ASCI port for US and Mega STe port. Of course.

Hi @DoG - you can tap it off of these pins in pink.

Screenshot 2020-06-27 at 12.38.24.png

[Icky]

So here are a few renders of the latest H5 revision.

Screenshot 2020-09-27 at 13.48.59.png

Screenshot 2020-09-27 at 13.48.19.png

Screenshot 2020-09-27 at 13.41.57.png

[JezC]

:goodpost:

Looking good - looks as if the MFP in the PLCC package is pretty much the only package change (other than the various logic/level shifters...most of which will be pre-fitted)?