TF CD32 Riser Revision 2 Design Complete

[terriblefire]

It seems that there is a steep learning curve for me ahead :)
I might need to test your patience with this a little.

I assume joy dat format would need to be the same like in mist?

Del bug - I had to forget to clear maybe_reset variable. Will do it next time I sit down in front of IDE.

The JOYDATX format is the same as Mist yes :)

http://amigadev.elowar.com/read/ADCD_2. ... e0038.html

I expect you're going to need me to tune the bus cycle stuff as this a tough tricky but if you get up and running with an interrupt routing i'll try and sort the rest. We can always go back to the old SPI mouse mechanism if we cant get this to work.

[terriblefire]

Here is an updated firmware (untested).

It does not care about the length of the ACK pulse. Anything from 10ns to 1uS will work. The firmware has smarts in it to not allow cycle overlap.

cd32_riserr1_main_top.zip

Maybe this timing digram will help?

Screenshot 2020-06-09 at 10.54.54.png

All you really need to do is ensure you put / grab the data from the data bus correctly and pulse ACK.

[arkadiusz.makarenko]

I wasn't able to boot CD32 with cpld firmware.

Outside CD32 I can see high on BUSINT all the time, now I am not sure if this is the reason why I can't trigger interrupt on this line, or I have other issues with my project. Need to test EXTI Interrupt set up on dev board.

And even if my cpld is ok. I completely can't remember where I got it from.

[terriblefire]

I wasn't able to boot CD32 with cpld firmware.

Outside CD32 I can see high on BUSINT all the time, now I am not sure if this is the reason why I can't trigger interrupt on this line, or I have other issues with my project. Need to test EXTI Interrupt set up on dev board.

And even if my cpld is ok. I complacently can't remember where I got it from.

You'll need to boot erased then flash when its running. Otherwise the machine will lock up on the first Mouse access. I could make it timeout after 32 clock cycles?

[terriblefire]

Here is a version that has a timeout after 32 cycles (approx 2uS)

After it counts to 32 it releases the hold on the amiga bus cycle and lets it continue normally

cd32_riserr1_main_top.zip

For your own diagnosis i've added this jed that will always put BUS_INT low (that is pin 22 on the CPLD).

cd32_riserr1_main_top_bus_int_always_low.zip

[arkadiusz.makarenko]

Here is a version that has a timeout after 32 cycles (approx 2uS)

After it counts to 32 it releases the hold on the amiga bus cycle and lets it continue normally

cd32_riserr1_main_top.zip

For your own diagnosis i've added this jed that will always put BUS_INT low (that is pin 22 on the CPLD).

cd32_riserr1_main_top_bus_int_always_low.zip

Thank you.

I managed to confirm that EXTI interrupts do trigger :) One less on my list todo.

Ok. So I will try to implement following
After receiving data from somewhere
1. Set high on INTSIG1
2. wait for interrupt on INSTBUS
3. put MSB section of data on D0-D7 big endian, I am not 100% sure why I need to check A0 (?)
4.Toggle INTSIG8 (PC13 - pin 2) and wait a little 100ns
5. put LSB data on D0-D7 ?
6. Change INSIG1 to Low.

[terriblefire]

Ok. So I will try to implement following
After receiving data from somewhere
1. Set high on INTSIG1
2. wait for interrupt on INSTBUS
3. put MSB section of data on D0-D7 big endian, I am not 100% sure why I need to check A0 (?)
4.Toggle INTSIG8 (PC13 - pin 2) and wait a little 100ns
5. put LSB data on D0-D7 ?
6. Change INSIG1 to Low.

1. INTSIG1 and INTSIG2 should be read during cycle to determine if its joydat0 or joydat1 being read. No need to output anything at this stage. we can make it fancy later.

3. You can skip checking A0 for word read/writes. However in theory something could read it byte by byte.

4. You dont need to wait now. The cycle can be as long or as short as you like. So long as the line actually gets low its fine. 10ns works.

6. changing intsig1 is not required. You just need to repeat 4. here.

You should probably check that BUS_INT is still asserted between 4 and 6 and just bail out.

you will need to put the D0-D7 back to input/highz quickly after the cycle is finished.

[arkadiusz.makarenko]

@terriblefire

I think I was missing one step at the beginning. I though that I need to do something to trigger BUSINT, but I should just wait for it to happen at this stage, and just act on it each time?

[terriblefire]

@terriblefire

I think I was missing one step at the beginning. I though that I need to do something to trigger BUSINT, but I should just wait for it to happen at this stage, and just act on it each time?

Exactly. You're emulating the JOYDAT0 and JOYDAT1 ports of the chipset. So when the CPU asks for the data you simply get interrupted and plonk the data on the bus and ack. The reason you'd check A0 and INTSIG1/2 is to make sure you're providing the right data for each request.

What the CPLD does is interpret the request from the CPU and raise an interrupt for you. Holding the bus long enough for you to respond.

Your mouse/joystick code needs to maintain two internal words for JOYDAT0 and JOYDAT1 in the main loop code. The interrupt code should respond to the CPU and supply the contents of these.

[arkadiusz.makarenko]

@terriblefire

I have some issues.
Firmware with 32 cycle release I do get interrupt, but each time I try to even reprogram GPIO for output PushPull or even set 0 as open drain, CD32 crashes.
For any other firmware I even don't register interrupt.

EDIT:
INTSIG1 and INTSIG2 should allways be 1...?

EDIT2:
I pushed changes.