Apologise if I appeared wanting to imply that and assure you: I didn't!
The problem (and advantage) of FPGAs is that you do not have access to raw silicon as the original blitter designers had. On raw silicon, there are possibilities you do not have on FPGAs (or you are at least not supposed to do unless you are asking for a lot of trouble), you are basically restricted to clean, synchronous design (you can't reliably design a delay based on gate propagation delays, for example).
Besides that you are restricted to the properties of the 'ingredients' the FPGA designers decided to put into your specific chip. You simply can't use any logic they didn't put on the chip upfront.
Bottom line is: you can't implement everything on FPGAs that you can on raw silicon.
But there is a workaround. You usually can implement a logically equivalent circuit with a clean synchronous design.
