The Megbusmaster development has started in earnest.
It is a no-mods-required installation and if using the two little clips going to the onboard 68000, it is in theory, solder-free too.
- IMG_0283.jpeg (279.54 KiB) Viewed 11 times
Unfortunately it's proven a bit of a pain to bring up so far.
The blitter seems *ludicrously* sensitive to anything loading the BR line. I have to both read from it (to pass it through to the external 68000 slot) and write to it when negotiating so it's declared an inout in my verilog and spends most of its time high-z.
However that's enough to stop the blitter working properly. Either freezing up on access (it'll boot to desktop and then accessing the menus locks up), or causing continuous arbitration cycles and thus seeing the blitter run in slow motion.
Setting all the CPLD lines to high-z and running the onboard CPU is still enough to cause the issue. Doing the same but disconnecting BR from the CPLD via the jumper bank there resolves it. So it's simply the connection that's enough to cause it.
So far I've tried adding another 10k pull up to the line -- no obvious effect -- and I'm thinking about trying a set up where I use two pins for BR. One to assert it (isolated via a diode) and one only to listen on it, mediated by perhaps a 1k resistor or something.
Otherwise, I'm not sure what to do? An external buffer before the CPLD? A much stronger pull up?
I'm tempted to remove the blitter and try to get everything else working first (the ACSI isn't happy yet either), but that seems just like putting it off.
Any thoughts electronisits?
BW.
