REMINDER - Stay logged in for at least 2 hours a week to get whitelisted.
Also it helps build a picture where our "good traffic" is coming from for detection scripts.
:o)
Have been hunting an ADC issue off and on and finally.. solved! :)
The sampled data was so catastrophically bad that my head was completely locked into thinking it _had_ to be my DSP code and me misunderstanding how to configure ESSI correctly for the i2s data stream.
But in the end, turns out I was missing series capacitor on the audio input to the ADC.
So.. traces cut, capacitors soldered in, and I finally have clean audio coming into the DSP from the ADC :)
Schematics, gerbers and so on which lives on Github has been updated with this fix.
And the external 128 kword SRAM for the DSP has now also been tested and verified working.
With DSP clocked at 90mhz it can do 1 waitstate access to 12ns SRAM so the bootup dsp code configures it for that timing.
agranlund wrote: 14 Jul 2026 21:44
And the external 128 kword SRAM for the DSP has now also been tested and verified working.
With DSP clocked at 90mhz it can do 1 waitstate access to 12ns SRAM so the bootup dsp code configures it for that timing.