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Next step for Phoenix chipset?

All the good stuff hardware and software wise for the Phoenix H5 series motherboards.
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olivier.jan
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Next step for Phoenix chipset?

Post by olivier.jan »

Just found out that aside from Tiny TapeOut, some other companies are starting to provide “affordable “ IC production. For example https://wafer.space/ has successfully raised money for a first production batch. Prices is 8500USD for 1000 chips, that’s not too bad. Interesting thing, the Global Foundry process used allows 5V…
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Re: Next step for Phoenix chipset?

Post by Icky »

Not bad at $8.50 a chip. Although considering the current chip pricing (sometimes x10) I expect it will be higher than that. I have been finding the FPGAs pieces have shot up. Was looking at getting some more Phoenix BLUEs and Phoenix Shifters manufactured but sourcing the chips has been a pain.

Also I think we would stick with FPGAs as we can update / upgrade the cores to fix bugs or add additional features.
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Re: Next step for Phoenix chipset?

Post by ijor »

Price per chip is, indeed, very affordable, but this is only as long as you actually are going to sell 1000 chips. For us, even 100 units seems too much. And this is assuming you get it right the first time, which is typically not the case. So if it doesn't work and you need to make a second revision, you have to shelf another USD 8500.

For certain "generic" chips, like legacy microprocessor, which could be demanded in high quantities, it could be an interesting option, tough.
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Re: Next step for Phoenix chipset?

Post by alexh »

What you've not factored into the price here is the NRE required to get to a netlist for this production run. The cost of the COT (customer own tooling) even 0.18um will be mid-high $100K range. You could get as close as you could possibly get with open-source tools such as Verilator, Icarus, YoSys etc. But to sign off you'd need comercial grade tools plus DFT insertion (scan/bist), place and route, static timing analysis and DRC checks.

And this price per chip doesn't include packaging. Packaging and test is a large part of the final cost of our (Kioxia) chips.

I've made a non-work custom chip before. I used the "hardened FPGA" route where you provided a working FPGA design and it is hardened by the FPGA vendor into a non-reprogrammable chip. This was a long time ago, 2005-ish. But it was much much cheaper than the NRE for custom silicon.
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