ST536NG build

[spen]

Lots of development effort has gone in to the STE536 accelerator board for the Atari STE and a raft of changes have gone in to the firmware. The result is it won't play nicely with the xc95144 CPLD that the older ST536 uses. The result is the cards we built last year can't easily run the new firmware.

I'm going to try to build a ST536 but with a Xilinx xc95288xl CPLD rather than the regular xc95144xl chip. This will be able to run the STE536 firmware under development. This was made slightly easier as exxos had a few dev boards half built and he let me buy some.

Basically the primary goal is to have a Mega4 + ST536 with all the new STE536 features. Without any weird adapters.
Secondary goals, debug issues en route and help move the scene a tiny step forward.

I'll try to capture everything so that anyone who decides they want to build the same, especially if this actually works.

I didn't know what to call the new card, so I called it the ST536NG. I'm sure somebody will set the record straight if there's a proper name!

[spen]

Here we go. Harry the Hamster dropped this off today

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Nice to see the rom socket pre-installed. That socket is evil to hand solder. I think I hate doing that more than the CPLD.

Bit of a way to go yet. More to follow, maybe at the weekend.

[coonsgm]

Excited to see how it goes. I have 2 ST536's that I'd like to do this for eventually.

[alexh]

a raft of changes have gone in to the firmware. The result is it won't play nicely with the xc95144 CPLD that the older ST536 uses. The result is the cards we built last year can't easily run the new firmware.

If it is simply about the HDL not fitting in the smaller CPLD/FPGA I am sure I could help optimise it to make it fit. I've got 30 years experience squeezing HDL into FPGAs that are not quite big enough. As long as it is not I/O or block-RAM limited there are things you can do.

Depending on the Xilinx toolchain / FPGA architecture removing the asynchronous resets from the HDL can have a big effect on timing and area. If this was an ASIC that would be an absolute no-no but because FPGAs registers are reset when they are configured there is no need for async resets. Sometimes simply changing the polarity of the reset from active low to active high can have a big effect too (depending on FPGA architecture).

Making sure your constraints are correct and not over/under-constrained. Using a different tool for synthesis and only using Xilinx tool for place-and-route can be a winner. Regularly get better results using Synplify by Synopsys to Xilinx synthesis tool.

Make sure that your clock generation (e.g. pin & PLL) configuration is correct so that the FPGA can use it's clocking resources correctly too can have big effect.

[exxos]

The compiler trims some down stuff already. But i couldn't get even a barebones system to easily fit in the 144. It ran out of registers mostly. But it struggled to compile any sort of barebones. I mean don't forget the original TF536 used the 288 anyway. I tried to keep costs down and use the 144 but it couldn't ultimately be done. Every code change threw out something else which needed even more tweaking. I was basically chasing my tail the whole time.

Most of the resources are used by the SDRAM controller. With even more code added, the compiler made it fit but then screwed up timings even more. Which I spent months trying to figure out why innocent changes broke random bits of the code. I kept tweaking that much until it fit and basically worked in the end. But I think some people had issues which may have been thermal related. I saw that a lot. Things where that sensitive.

Now I know of those issues, I then found even more issues which used up even more resources to fix. I posted loads about it in the STE536 thread. Basically I'm using around 80% of the 288 now and I've not even got everything I want in there yet. A lot of stuff is dumbed down to save registers, which may be part of some current problems. So I may struggle to fit it all in a 288, nevermind a 144.

People will have to change the PLD if they want to continue with firmware updates.

[ijor]

Depending on the Xilinx toolchain / FPGA architecture removing the asynchronous resets from the HDL can have a big effect on timing and area.

Didn't you mean synchronous by chance, or did you really mean asynchronous ? Because on most FPGA families async reset it's "free". It's there already at the hardware you use it or not. Yes, you still have to route the signal, and if you have many different resets, that could be an issue. But otherwise?

... but because FPGAs registers are reset when they are configured there is no need for async resets.

I don't want to hijack the thread, but I don't think it is a good idea to rely on the powerup/configure builtin reset. In latest generations this is even more critical.

[spen]

I don't want to hijack the thread, but I don't think it is a good idea to rely on the powerup/configure builtin reset. In latest generations this is even more critical.

It’s cool. I’ve got the Xilinx toolchain and perhaps 5% of the knowledge of a hdl engineer. I’m happy to go to 6%

Alexh - agreed. It’s not straightforward. Just trying to explain in simple terms in the intro why I’m throwing time and energy at this project. Thanks for the wisdom.

gotta love the internet. The soldering iron isn’t even warm yet and we’re in to verilog. Thanks for the input guys.

[exxos]

I had a thought just that the STF has that "sound bug" which I don't think the STE had. So it's likely the STE firmware won't work on the ST536. It will probably crash early on after power up. Likely when it tries to access the PSG for sound or floppy.

The V1 firmware on the STE firmware page is the closest to the original ST536 firmware. So maybe best start with that. However I should be able to patch up a more suitable test firmware tomorrow. But have no way to test anything yet.

Like I mentioned somewhere, don't use mono mode or the IDE port as something might be bugged there.. But it only currently shows faults on @Badwolf's STE. I wasnt able to replicate here. It might only be a problem on the STE.. No idea..

I didn't know what to call the new card, so I called it the ST536NG. I'm sure somebody will set the record straight if there's a proper name!

Rev 5.50 pretty much can't even remember the previous build number. Think it was just 5.0. Should have probably gone to version 6 to start with the 288 PLD. Maybe I'll do that on the production run if it ever happens.

[spen]

Well, that was quite a break. The TLDR is I have a nice new job, 3 weeks in and ready to roll!

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This is where we left off, Exxos had removed the old CPLD before shipping. There's quite a bit of hardened flux and the whole thing is as sticky as a jam sandwich without bread. Fortunately there is a quick solution.

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The saponifier dissolved the flux in a few minutes with two applications. It doesn't smell nice and it's probably bad for your skin, your lungs and your cat. It has a skull and crossbones on the other side. It is very good at removing flux though

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Then some IPA followed by distilled water. A vast improvement. The pads were a bit lumpy with old solder, so I ran over them with a wick and some flux.

[spen]

The 144pin quad flat pack is fairly painful to solder, it requires patience and high powered reading glasses. And a microscope.

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This is the view! Looking at the screen and not your hands or the workpiece takes some getting used to.

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Solder is top quality for this job, tin / copper and 0.3mm diameter!

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This was pre removing the lumpy solder on the pads! The stage of placing the chip exactly right takes ages, or at least it does for my hands. I'm no surgeon.

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Once lined up apply a pound coin and a lot of flux. Pin the four corners by soldering each corner pin.

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Then carefully solder each pin.

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That's what it should look like - I promise it's not bridged, its the flux reflecting light (yeah I just set myself up for a massive fall). It received another clean with the saponifer, IPA followed by a trip to the parts wash overnight. The saponifer turns the flux to soap and you've got to get it all the soap off or it will look terrible as it ages.

That's it for today. Back tomorrow when I'll test it to see if the JTAG chain is intact and it is recognised.