This does appear to be the same effect: short push OK, long push, errant pulses.
My initial analysis suggests to me that basically the circuit is trying to ensure a minimum reset pulse width after a button push. That seems to be around 300-400ms.
A push shorter than that will keep RESET (and HALT) asserted until C1 is charged past the threshold voltage and then RESET can be released. That's the 300-400ms period.
A push longer that that, however, allows C1 to be charged past that threshold already when the button is released. At that point the deassertion of the output can happen instantly.
BUT that means any bouncyness or scratchyness in the reset button that gets past the open-collector NOT gates at the beginning of the circuit will be transmitted through to the RESET line until C1 has discharged sufficiently to break the cycle again. And I think that's what we're seeing here.
I'm not 100% sure what C7 brings to the party. On the face of it all it appears to do is tax the upstream NOT gates' current sinking ability. It seems to fill and drain too quickly to have much influence over anything else.
I don't know enough about 555s to see if there's a quick way to only start filling C1 when the reset switch is relased (changing its behavior to assert ~300ms after reset is relased), but for now I'll put that down as a bad job and move on to what that RAM test is telling us.
Good shout. I don't know much about the Falcon's ST-RAM interface, so I'd better get learning.
From what I can tell about the diagnostic cart's output, however, each of those lines represents a bit failure when writing zeros to a single address, namely 0x8. Since the memory connector is 32 bits wide I'm guessing each one corrsponds to a data line on the memory connector (athough that's obviously not true on the ST range where it's presented the same way, so I may be barking up the wrong tree).
The spectacular number of ones in that capture (which came from a known working card) implies to me that it's likely something centralised rather than a bad pin contact on the header or a pair of shorted contacts. RAS and CAS would certainly fit that bill, so I'll be taking a look at those when I can. Thanks.
There don't appear to be many other candidates to investigate on that path. VCC, Ground and MADDR, I suppose. MDATA seems to be a direct connection without buffering or filtering to VIDEL.
One nota bene, I did also get a couple of I2 RAM Disturbance messages (0x8 and 0x67E, IIRC). The fact it's only two is interesting, though, as the service manual seems to imply there should be 2040 tests done at the I2 point.
Also I should note that it takes a lot of resets to get any output on the serial port. I was actually testing the the reset pulses when I changed windows and noticed I'd generated something there. Again, that to me suggests the RAM is perhaps required to get to the screen output point and is obviously not *completely* toast, although that may be wishful thinking.
Thanks Steve. I've not got around to checking those yet, but that one and the NVRAM are in my mind.SteveBagley wrote: 17 Aug 2025 23:49 Not having the 500kHz clock to the keyboard ACIA definitely caused my Falcon to fail to boot when I tried to fit a Nemesis upgrade last year
BW
