Phoenix Nexus FPGA board

[PhilC]

Bungle Blitter
Zippy MMU
George Glue

And you could call the PCB Rainbow

[exxos]

And you could call the PCB Rainbow

Nobody even noticed yet the acronym for my new 206 decoder is actually BUGGER or something like that.. I foget

[coonsgm]

I did call out these efforts to replace the custom IC's on my latest YT video

Thank you all for the awesomeness!!

[exxos]

I did call out these efforts to replace the custom IC's on my latest YT video

Thank you all for the awesomeness!!

[ijor]

I'm with a bit of a flu. Can't exactly do high tech stuff at this time. But I keep being amazed by the wisdom and inspiration of this forum. Please continue!

[sporniket]

Not very original PhœMMU, PhœGLUE, PhœBLIT ; all names truncated to 2 syllabus for better smoothness (PhœBLITTER seems a bit rough). And with a liggatured 'œ' glyph, not "o" followed be "e", of course.

Edit : most likely inspired by Batman and all of his "bat-something" gadgets

[exxos]

All good suggestions.

The hyper blitter is a play on words from Intel's "hyper transport" as the blitter will have a similar feature.

[exxos]

I'm with a bit of a flu. Can't exactly do high tech stuff at this time.

Hope you feel better soon. My girlfriend and I don't feel great because of the heatwaves in the UK

But I keep being amazed by the wisdom and inspiration of this forum. Please continue!

[exxos]

I'm still working on the PCB in the background. Likley will be next year before anything physical appears..

But I want to also gauge how many alpha boards to produce. I'll either get 5 or 10 made. I can't say on cost. But could may well be around the £200 mark.

It will need testers who are able to remove the MMU, BLITTER, GLUE sockets and fit headers to insert the new FPGA board. The H4 should be easy as users built them. The H5 mostly had leadfree solder, so extra care and skill will be used as to remove the sockets.

The board will replace the MMU, BLITTER, GLUE with @ijor's cores. It should give 14MB ST RAM. So no need for altram. The cores should be able to run at 16mhz and hopefully 32mhz. It will be a true speed boost where ST RAM will also run at faster speeds. That's always been a problem with add-on boosters. But we won't have those issues.

We plan for the BLITTER to run at much faster speeds. Not just limited to whatever the bus speed normally is, EG 8mhz. BLITTER will have direct access to RAM and could be clocked at speeds up to 128mhz.

Myself and @ijor are discussing various other ways we can modify the architecture to make various other speed improvements.

I think the Phoenix platform will soon, and finally, get the High speed dream as realised a few years back

[JezC]

I'd be happy to help with testing.

With a couple of H4 boards and 4x H5 of various versions I should be ok with removing/replacing sockets and fitting headers.

I hope to be able to support you with an alpha board as well...