The Phoenix Nexus board will be a FPGA plug-in board to fit the H4 / H5 series motherboards to replace the blitter, GLUE, MMU with FPGA cores.
The project branches from the other thread such as recreating the chips in FPGA . @Icky and @ijor are currently working on finishing the testing of the cores individually to make sure we have a totally accurate individual core.
I feel this work is important as only combined cores exist in other projects such as the MiST. But these are not really full cores which will "drop in" to a original machine and work. So we aim to have true cycle accurate cores very soon.
BLITTER
viewtopic.php?f=80&t=79
GLUE
viewtopic.php?t=7338
viewtopic.php?t=2536
MMU
viewtopic.php?t=2478
viewtopic.php?t=7312
Early work was using the Suska cores (with Wolfgang's permission) but we ran into various issues where later @ijor took over to develop better cores for the project.
Its aim is to replace the blitter (or simply add a blitter as they are hard to find and expensive) with a higher speed version with the possibility of adding more features at a later date. We can run the blitter at even higher speeds than the CPU. This not only does blitting many times faster, it will reduce the "hog time" of the bus giving the CPU more time to do stuff as well.
The original MMU wasn't stable with the "double overclock" which lead me to abandon that direction completely. More so as it will be a lot of work in solving all the problems just to basically hit a brick wall because there is simply no "whats next" aspect to it. It's essentially a dead-end project right from the start. So recreating the MMU means we can fix all the issues while aiming to remain fully backwards compatible and cycle accurate with the original chips.
The good thing is that we can inherently run these cores at almost any speed we want. The first step of the project is to simply replace the three main chips and run them at stock speed. The second phase of the project is to run 16MHz (likely with the motherboard simm) and later push to 32MHz bus with onboard SDRAM.
The main bottleneck in any ST system is always switching back to 8MHz to access the ST side stuff such as video RAM etc. It's why accelerators have "TTram" as the CPU can access that RAM at 50MHz or whatever. However, performance is crippled with anything which is having to access STram or video RAM. So the aim of the new chipset is to remove that limitation and simply have a faster bus of 32MHz.
Because we are recreating the chips, we can fix the 4MB STram limit and go for 12MB for example. We can fix DMA issues , including the blitters current limitation of 4MB memory access. We can simply fix everything and do things properly. No need for endless hacks with everything!
The faster bus opens the door to more "video bandwidth". This means higher resolutions or colour depths are possible with the reworked shifter. Is no need to hack on graphics cards or whatever, it will all be a evolution of the original ST design.
I certainly believe exciting times are in the near future
