Let's build a CTPCI!

[dml]

Have just gone through this thread again and I now see that someone else complained about the .zip containing only two layers - and informed that it was a work in progress. :) so that explains quite a lot.

[edit - nope]

Have finally got some time to focus on this more properly, re-read everything and figure out whats going on. It does seem like a coincidence that two different viewers show missing layers but it can still be a problem with the viewers... Will see if I can get at least one of them to resolve all 4 layers from the current archive first.

I'll report back when it begins to make sense.

[foft]

See the Altium Gerber layer names, they match what I put in the zip file:
https://www.candorind.com/blog/gerber-f ... comparison

Filled in here for future reference in case that link dies one day!

File extension	layer
drl	Drill
g1	Inner copper 1
g2	Inner copper 2
gbl	Bottom copper
gbo	Bottom silk
gbp	Bottom paste
gbs	Bottom solder mask
gtl	Top copper
gto	Top silk
gtp	Top paste
gts	Top solder mask

[dml]

So i have submitted for review on both JLCPCB and PCBWay, just for lols.

JLCPCB detected 2 layers and identified them all as shown in the attached image. Each layer correlates to 1 file in the archive. Yes, it does seem like layers are missing but are there missing files? Or are there multiple layers in some individual files? I'm assuming it has to be the latter.

Screenshot 2025-03-27 at 19.48.11.png

PCBWay didn't detect anything (yet). I had to enter all the info first then upload the gerber archive only afterwards. It's under review and it doesn't seem like I can see any results until that's complete.

Not optimal, but not much else I can do until that finishes.

I did hack around with the gerber files to see if I could do the rename thing described earlier in this thread but it made no difference in gerbview.

[dml]

See the Altium Gerber layer names, they match what I put in the zip file:
https://www.candorind.com/blog/gerber-f ... comparison

Oh right - I'll have a look at that table, thanks.

[edit]

Looks like the entries for 'inner' layer translation is blank for KiCad...

[update]

JLCPCB just complained that the board has 4 layers... so.... I guess... that's fixed?

(gerbview.... ->trashcan)

[dml]

So I received a set of new PCBs for both the CTPCI and the PCI connector board.

Given all the earlier confusion over:

- layercount & inner layer visibility (when I last tried, at least)
- gerber file naming/formatting & expectations for different software
- less-than-certain 1:1 match with previously manufactured batches (this was a new order with some potential for errors, not a repeat of someone else's successful order!)

...I'm looking for a way to confirm the inner layers exist and are correct on these new boards before I go ahead and potentially waste good parts on them.

I know the top/bottom layers are on the correct sides because the silkscreens are correctly flipped and in the correct position relative to the solder pads for the main ICs.

I would normally just look at the layers and do some continuity testing but layer visibility is one of the uncertainties. I'll look for another way to view the gerbers but it would be helpful if anyone (foft?) could point out pads which require inner layer connections to confirm a few are correct.

I suppose I can maybe do this by looking for a via that appears to go nowhere in the gerbview and locate it in the schematic, then find where it is supposed to go. a bit tedious & error-prone but might be enough if I can prove a couple of those are good.

[edit]

I'm in no hurry to build this - there are some other problems I need to sort out before I'd be able to do anything with it (!)

[dml]

Tried the gerbers in Altium's viewer today. Same result.

Top and bottom layers have traces. 'mid 1' and 'mid 2' are also identified as copper and treated as inner layers - but they don't contain traces, just dots (vias). No connections across the layer plane.

Screenshot 2025-04-09 at 17.28.30.png

Is this how these inner layers are intended to be? Or is this still incorrect? I can't use the result above to do any kind of verification of the PCB because there are no traces to follow here.

I'll try using the table shared earlier in the thread to change the filenames and will try other viewers but so far I'm consistently seeing 2 'inner' copper layers containing nothing but dots.

[dml]

For example, this bothers me. A pad which goes 'into' one of those mid layers and goes nowhere. Doesn't route anywhere else on the front or back via the middle because the middle layers appear to be nothing but vias from either top or bottom side and not outgoing traces.

I can see other cases like this so I have to assume this is not a complete representation. Yet 4 copper layers are registered.

Screenshot 2025-04-09 at 17.38.57.png

[dml]

I think maybe I have figured out what is going on. The views are correct but my interpretation of what could be in those layers is wrong (and lacking any other good information, maybe have now guessed my way to success).

The 'inner' layers here are not meant to be signal layers but are power and ground plane fills. The dots are vias leading the top/bottom to those planes. The planes themselves are 100% fills which makes them difficult to see.

It's weird that the dots or holes are in the layer fill colour and the 'planes' are empty/blank/background colour... but whatever.

I can at least now go ahead and confirm that with some checks but it would explain a lot.

[edit]

Yup, have been able to confirm the inner planes are power/ground by beeping out the pads of various decoupling caps to each other, which have no top/bottom connections. They are joined by the inner planes.

Looks like I'm un-stuck, at least for the building work...

Screenshot 2025-04-09 at 18.17.42.png

[dml]

Does anyone happen to have decent, high-res photos of the CT63, CT60, CT60/e boards? Topside in particular, plan-view.

All I can find online are fuzzy 2000's webcam photos with JPEG compression at <65%. I could use something where I can see details.

:p

(oops this was meant to go in the other CTPCI thread, nvm!)

[viking272]

Does anyone happen to have decent, high-res photos of the CT63, CT60, CT60/e boards? Topside in particular, plan-view.

This is a CT63 with original cpu and fan from Rodolphe. Plus a CT60e from Willy as it was handy!

20250709_124957.jpg

20250709_125336.jpg