exxos wrote: Mon Mar 17, 2025 4:00 pm
I wonder if the Winbond chip being 200mhz, actually need something close to that frequency to reliably work.. Whereas the alliance chip being a slower part of 166 MHz, may tolerate the down clock more (100MHz)
No. There is "virtually" no minimum frequency. I say "virtually" because if you use extremely low frequencies you might violate some specifications, specially of course, the minimum refresh period. 100 MHz is not considered a low frequency at all, in this context.
... slightly faster.. which should work better.. in theory.. as timings shouldn't need to be as tight
That's not exact. A faster chip will usually require both smaller setup and hold timings. That means, indeed, that the
output timing (from the controller to the DRAM) would be less tight. But a faster chip will also typically provide less output hold time. And that means that the
input (to the controller) timing could be even tighter! Faster is not always better.
it seems incredibly weird that the winbond chip seems to have a very narrow timing window of like 3ns.
it also begs the question, that if the inverted clock worked better for the winbond, should we continue using that clock, or go back to the tried and tested (original) TF536 timing..
I don't know what was the original T356 timing, but in general it depends on the frequency. For lower frequencies inverting the clock is better, Or at least is simpler. At higher frequencies you might need a more fine adjustment. Ideally you need a PLL to shift the clock to the optimal relation.
But, most important, you need to perform a timing analysis. At lower frequencies you can get along just by inverting the clock. At higher frequencies an inverted clock might produce setup timing violations.
Probably (but again, only a timing analysis would tell), 100 MHz is too high for working with an inverted clock.
I look back through my previous conversations relating to the clock inversion, and I mentioned before that even "innocent" changes to the code seemed upset the SDRAM controller..
Yes, that's very possible. Unless you register all the DRAM signals (which is not always possible), your timing depends on the actual compilation result. That's why timing analysis and, if available, timing constraints, is so important.
