A2000 help please

[Steve_w]

Not having the buster in the socket does not hinder the startup of the machine.
It is a shame that PCB explorer does not have a A2000 schema.
(Maybe the A500 one can help a little if it is a rev 6 A2000?)

I agree, I find that very helpful in troubleshooting, shame I cant help them create an a2000 page. I thought it useful to state Buster was not present as I think that can cause bus conflicts if faulty.

My board is rev 4.3, I just changed J101 as that was set in position 2-3, for the 8371 Agnus I believe it should be in position 1-2.

The jumpers are set as follows

J101 Set to 1-2 for 8371 Agnus
J102 Open - I believe this set PAL
J300 Set to 1-2 (TICK from PSU) as you rightly said Maximilian, as I have the original PSU the TICK is generated from the PSU. it was set to 2-3.
J500 closed

On power up I see about 4 or 5 square waves on the data/address bus momentarily (does this indicate 4 or 5 bits of data on the bus?) then nothing.

After the initial 4 or 5 square waves the scope shows this

D1-4 - 3.7v (is this classed as "floating"?)
D5-8 - 90mv
D9-12 - 3.7v
D13-16 - 90mv
A1-6 - 100mv
A7,8 - 4.1v
A9-11 - 100mv
A12-13 - 4.1v

Trying to see if there is pattern that may indicate a faulty logic chip, the data bus is grouped into 4 high, then 4 low, then 4 high, then 4 low, looking at the schematics that would implicate all 6 logic chips (U103, 104, 105 and 106, 603, 604).... scratching my head a bit now.

[stephen_usher]

As mentioned in another post about resurrecting a machine, the 68000 after reset will blindly do four reads to set up the CPU and then it will try to read an instruction to start processing.

You have activity only for this time, which suggests maybe a bus arbitration line problem, if the CPU hasn't halted.

Check on the CPU is the /HALT is low if it is then the CPU won't be doing anything.

Check to see (after reset) if there's any activity on the /DTACK line, by setting your oscilloscope to trigger on a falling signal and do a one-shot capture.

P.S. Actually it was the thread on your 500+ I was referring to. Follow the same procedures outlined there. The A2000 is essentially the same machine in a different form factor.

[Steve_w]

As mentioned in another post about resurrecting a machine, the 68000 after reset will blindly do four reads to set up the CPU and then it will try to read an instruction to start processing.

You have activity only for this time, which suggests maybe a bus arbitration line problem, if the CPU hasn't halted.

Check on the CPU is the /HALT is low if it is then the CPU won't be doing anything.

Check to see (after reset) if there's any activity on the /DTACK line, by setting your oscilloscope to trigger on a falling signal and do a one-shot capture.

P.S. Actually it was the thread on your 500+ I was referring to. Follow the same procedures outlined there. The A2000 is essentially the same machine in a different form factor.

HLT is high so CPU should be running.
DTACK is high, with some initial activity before staying high again.

How would I setup a one-shot capture?

Thanks

[stephen_usher]

How would I setup a one-shot capture?

On my Hantek I have a button called "Single Seq", but it will depend upon your oscilloscope.

Well, it's good that you seem to have activity on the /DTACK line, so that suggests the read cycles are doing something.

Has the /BERR line gone low? (This would suggest a bus error.)

Have you buzzed out all the address and data lines between the CPU and the ROM? How about the address lines and GARY?

When you power on does the /ROMEN line on the ROM go low at least four times? This line is controlled by GARY. As we discussed with you A500+ GARY is the key to all hardware addressing including enabling the ROM.

These are the basic steps to take on any Amiga as without these working nothing will. It's the simplest part of the Amiga as the ROM, GARY and CPU are the only things that side of the buffers/transcievers.

[Steve_w]

How would I setup a one-shot capture?

On my Hantek I have a button called "Single Seq", but it will depend upon your oscilloscope.

Well, it's good that you seem to have activity on the /DTACK line, so that suggests the read cycles are doing something.

Has the /BERR line gone low? (This would suggest a bus error.)

Have you buzzed out all the address and data lines between the CPU and the ROM? How about the address lines and GARY?

When you power on does the /ROMEN line on the ROM go low at least four times? This line is controlled by GARY. As we discussed with you A500+ GARY is the key to all hardware addressing including enabling the ROM.

These are the basic steps to take on any Amiga as without these working nothing will. It's the simplest part of the Amiga as the ROM, GARY and CPU are the only things that side of the buffers/transcievers.

Yes ROMEN has some activity on power up (my 1st post detailed some of this), BERR is high and stays high. I've tested continuity on address and data lines between ROM, CPU and GARY and all good. I tested continuity on /AS, UDS, LDS, R/W, DTACK, ROMEN, OVL. OVL is high.

[stephen_usher]

You're getting very close to needing a logic analyser now.

From what I remember, the first thing that the diagrom does is try to access the chip running the serial port. Have you tried swapping U300 and U301?

Actually, before that check the CS pin (23) on U301 to see if that does anything. Also buzz out D8-D15 between that chip (pins 33-26) and the CPU along with A8-A11 to pins 38-35.

[Steve_w]

You're getting very close to needing a logic analyser now.

From what I remember, the first thing that the diagrom does is try to access the chip running the serial port. Have you tried swapping U300 and U301?

Actually, before that check the CS pin (23) on U301 to see if that does anything. Also buzz out D8-D15 between that chip (pins 33-26) and the CPU along with A8-A11 to pins 38-35.

I've swapped 300 and 301, no change. .

Yes maybe the CIAs are not being selected due a fault in a logic chip. The a500 uses A12 and A13 as well as VMA add inputs into a logic chip to select odd/even CIA.

Good idea, I hadn't thought of this, I'll check CS and the data and address pins from the CIAs to CPU tomorrow

[Steve_w]

Good spot regarding CS on the CIA I forgot about that. I found a break between the CPU and U302 on the VMA trace, so fixed that as VMA along with A12 are inputs into U302 with the output being CS for pin 23 on the CIA U301.

I now see two square waves on pin 23 on U301 initially then it stays high.

D1-16 across the CIAs sound out okay with the CPU as do A11-8.

[Steve_w]

You're getting very close to needing a logic analyser now.

From what I remember, the first thing that the diagrom does is try to access the chip running the serial port. Have you tried swapping U300 and U301?

Actually, before that check the CS pin (23) on U301 to see if that does anything. Also buzz out D8-D15 between that chip (pins 33-26) and the CPU along with A8-A11 to pins 38-35.

looking at your post on my A500 help post, as you said it looks like this A2000 is getting to point 2 in the sequence and then not progressing. Could it be there is a problem with an address or data bus logic chip stopping code from the ROM executing?

The sequence is:
1. Reset goes high.
2. CPU then does four read cycles of 16 bit words starting at address 0x0 and incrementing the address each time.
3. CPU uses this information to read the first instruction from the address read from the first four reads and begin execution.

A simple 16 bit read cycle would be:
1. Put the address on the address bus.
2. Set R/W to read.
3. Lower /AS (Address Strobe) to tell the system that there's a valid address on the address bus.
4. Wait for /DTACK (DaTa ACKnowledge) to go low, telling the CPU that the data on the bus is ready.
5. Read the data from the data bus.
6. Raise /AS.
7. Wait for /DTACK to go back up.

[Steve_w]

I just worked out how to set up single shot trigger capture on my scope, a really nice feature, every day is a school day :-)

Here is AS

AS.jpg

ROMEN

OVL.jpg

DTACK

DTACK.jpg