TF4060 Beta Program

News & updates for the upcoming 68060 accelerator

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Chritoph
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Re: TF4060 Beta Program

Post by Chritoph »

So... as suggested, I tried Frankenstein's versions of the firmware in 3000T.

2024-05-09 bus jed combined with 2024-06-12 ram bin does not lock up on first SCSI access but trying to boot my SCSI boot partition says "Not a DOS disk...".

2024-06-12 bus jed combined with 2024-05-09 ram bin locks SCSI up on first SCSI access as before.

Back to all 2024-05-09 firmware and my SCSI boot partition magically came back to life.
terriblefire
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Re: TF4060 Beta Program

Post by terriblefire »

I have a theory of what might be going on.

Essentially I think the A3000T might be requesting a line transfer whereas all the other machines do LONG. In the original fw that works it was hard coded to be LONG transfers all the time. But the new fws allow byte or word transfers. However i've not taken LINE into account (overlooked it as i have not seen anything try that so far) and that might cause complete chaos.

So i will provide a test FW. Those with A3000T/A4000T can try it. It will not be "production" but i'd just like some feedback on whether it works or not.

Essentially all i am doing is blocking burst to SDRAM when DMA is in flight. It cannot burst when DMA is happening anyway as the clock speeds are 4x different at best case.
tf4060r5_18533_2024_08_21_121f718_alpha.zip
EDIT: Tested on A4000CR with Fastlane Z3. Stable AF
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"It is not necessarily a supply voltage at no load, but the amount of current it can provide when touched that
indicates how much hurting you shall receive."
terriblefire
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Re: TF4060 Beta Program

Post by terriblefire »

OK i am going to revise a previous statement. I cant find exactly where it is but its in this thread somewhere. I was wrong.

I thought i had tested the Z3 Fastlane DMA-ing into the 0x1xxxxxxx range but it turns out the transfer i asked for was below the size threshold for the driver to perform a DMA transfer. Grrr.

When i try it with over 2048 (not sure exactly what the threshhold is) then i get a hard bus hang.

So the question is what to do with the upper 128Mb?
———
"It is not necessarily a supply voltage at no load, but the amount of current it can provide when touched that
indicates how much hurting you shall receive."
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Chritoph
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Re: TF4060 Beta Program

Post by Chritoph »

Remind me...
Can't a memory node be marked as non-DMA capable?
Is that correctly respected by the OS if yes?

Edit: nope, only "24bit DMA" yes/no.
:(

Edit again: start with 128MB only and allow adding the extra 128MB manually "later" if the system has no DMA master.
Doesn't the partition's transfer mask allow to prevent using memory in the area above e.g. 0x1000 0000?
terriblefire
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Re: TF4060 Beta Program

Post by terriblefire »

Chritoph wrote: 21 Aug 2024 15:36 Remind me...
Can't a memory node be marked as non-DMA capable?
Is that correctly respected by the OS if yes?

Edit: nope, only "24bit DMA" yes/no.
:(

Edit again: start with 128MB only and allow adding the extra 128MB manually "later" if the system has no DMA master.
Doesn't the partition's transfer mask allow to prevent using memory in the area above e.g. 0x1000 0000?
1. You could fix this with the transfer mask yeah. But i feel like thats something people wont do. Although we could put a test in and recoverable alert if we detect it.

2. You could also fix this with a U714 jed update so the DMA cycles make it to the 030 bus.

3. You could try and cram the ram in the lower area between 0x01000000 to 0x6FFFFFFF ( you'd lose 32 mb) .

What you cannot do is make this a Pseudo Z3 card.

EDIT: I have confirmed things work fine with the z3 fastlane if you set the mask to 0x0FFFFFFF
———
"It is not necessarily a supply voltage at no load, but the amount of current it can provide when touched that
indicates how much hurting you shall receive."
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Chritoph
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Re: TF4060 Beta Program

Post by Chritoph »

EDIT: I have confirmed things work fine with the z3 fastlane if you set the mask to 0x0FFFFFFF
Would be good enough for me.

Do the DMA requests arrive at the CPU slot, if you do (3)?
Are you sure? Did you test it?

Maybe that is the most maintenance free option then.
And allow manually adding the remaining 32MB for ppl like me who are fine with that mem mask approach and know what they are doing.
Oliver_A

Re: TF4060 Beta Program

Post by Oliver_A »

There must be more to it, because, again, I can confirm that copying more than 128MB of Data to Ram Disk with the A4091 works, no hang-ups, data integrity is correct.

Another thing: why should A3000T DMA behave differently than A3000? Same Buster, same DMAC, same Gary, same Ramsey.

It‘s the effing timing / DMACs sensitivity to the handshake signals.
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Re: TF4060 Beta Program

Post by terriblefire »

Chritoph wrote: 21 Aug 2024 20:08
EDIT: I have confirmed things work fine with the z3 fastlane if you set the mask to 0x0FFFFFFF
Would be good enough for me.

Do the DMA requests arrive at the CPU slot, if you do (3)?
Are you sure? Did you test it?
Yes and Yes. Because the U714 will not decode that address.
———
"It is not necessarily a supply voltage at no load, but the amount of current it can provide when touched that
indicates how much hurting you shall receive."
terriblefire
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Re: TF4060 Beta Program

Post by terriblefire »

Oliver_A wrote: 21 Aug 2024 21:04 There must be more to it, because, again, I can confirm that copying more than 128MB of Data to Ram Disk with the A4091 works, no hang-ups, data integrity is correct.

Another thing: why should A3000T DMA behave differently than A3000? Same Buster, same DMAC, same Gary, same Ramsey.

It‘s the effing timing / DMACs sensitivity to the handshake signals.
Very interesting.
———
"It is not necessarily a supply voltage at no load, but the amount of current it can provide when touched that
indicates how much hurting you shall receive."
terriblefire
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Re: TF4060 Beta Program

Post by terriblefire »

Without getting a 3000T mobo to use for test i don't think i'm gonna find this
———
"It is not necessarily a supply voltage at no load, but the amount of current it can provide when touched that
indicates how much hurting you shall receive."

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