Level shifter - fast enough for ST ROM chip enable?

[AAG]

Hi all - 1st time posting here - hoping might get some insights/not sure where else to ask!

Short story is I'm trying to interface with ST cartridge port to a micro controller.

My 1st though/hurdle to overcome would be making sure can use a level shifter with chip/output enable to respond within the time

Using a SN74LVC245A / attached to cartridge port via breadboard

overview.png

Use a HOBBY COMPONENTS USB 8CH 24MHZ 8 CHANNEL LOGIC ANALYSER - I can see the ROM select does low for ~290 ns, then high, then low again. BUT the output of the chip doesn't "keep" up.

D1 - Rom select
D3 Chip output

timings-1.png

Using a SN54AHCT125 I got same kind of result

timings-chip2-no-cap.png

But adding a ceramic cap on the VCC was much better

timings-chip2-b-capvcc.png

I did try adding a cap with the SN74LVC245A (and had DIR tied to ground which swaps directon from Bx to Ax but can't get the SN74LVC245A to respond fast enough.

Having individual channel selects on the SN54AHCT125 is overkill.

Any suggestions? (May try solder/"Perma-Proto Breadboard"??)

Thanks in advance

[Cyprian]

have you seen SidecarT (RPi connected to the ST Cart port)? Maybe there you can find an answer.

https://atari-forum.com/viewtopic.php?t=43073
https://sidecart.xyz/
https://github.com/diegoparrilla/ataris ... berry-pico

[AAG]

Thanks - (yes i am on the waiting list.)
But I'd already started something similar with esp32 and think mu issues ate due to timings as the real basic example shows.

From a pure learning point of view, is like to try and get/learn why the logic output isn't keeping up.

Thanks

[JezC]

I might have missed something here...but without the schematics of what you're connecting it's hard to tell.

Do you have external pull-ups on the data lines? I'm wondering how long the signal is taking to go high when the output enable is removed.
If it's straight into the pins on a modern micro then their internal pull-ups are typically tens of k ohms & so it can take a comparatively long time to pull the low signals high again.

Either try fitting a lower value (maybe between 1k and 5k) pull-up or check the real signal level with a 'scope to see how fast the rise time is.

Anyway, welcome & good luck with your project - it sounds very interesting!

[chronicthehedgehog]

Is your esp32 3.3v?

If so you might have more luck with the SN74LVC4245A which also does 5v to 3.3v level shifting. The SN74LVC4245A switches in under 10ns. I think the SN74245A is similar.

Cartridge projects seem popular at the moment. I started one a few weeks ago also. Maybe it's the moon or something :D

EDIT:

Just remembered you can't get 4245s as DIPs for breadboards. You'd have to get some adapters and solder them yourself. I had these made a while ago, sadly I ebayed those I didn't need. Maybe something else is available

IMG_20220530_173838 - Copy.jpg

[sporniket]

Seems that the capacitor you have added was in fact the decoupling capacitor that should accompany any IC on a circuit.

e.g. on the datasheet of the SN74LVC245A : https://www.ti.com/lit/ds/symlink/sn74lvc245a.pdf , see section #11 "Power supply recommendation" (emphasis is mine)

Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1 μF capacitor is recommended. If there are multiple VCC terminals then 0.01 μF or 0.022 μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of
noise. The bypass capacitor should be installed as close to the power terminal as possible for the best results.

Also, the "typical application" section usually does not forget to put the decoupling capacitor.

Now about the SN74LVC245A being unable to cope even with the capacitor, I have no idea, as the timings stated in the datasheet are rather quick.

[ijor]

What's wrong with a simple 74HCT244? Should be more than enough. You have plenty of time both to enable and disable the output.

Do you have external pull-ups on the data lines?

He is reading from the cart to the cpu bus, not the other way around. Cart port is read only.

[exxos]

I think we need a proper schematic as with all one side connected to 0v then ROM CE and dir are kinda irrelivent as inputs are all 0v or outputs are shorted to 0v regardless.

But looking at your timings , both go low at the same time, so don't don't see a problem there. Then later the timings are off like your measuring a address pin on the ST bus where ROM CE will not pulse all the time anyway as the CPU doesn't talk to the port every bus cycle.

So looks like your measuring a address or databus signal and maybe a ROM CE signal. It's hard to really tell.

Any logic buffer will likely be less than 20ns delay. It's nothing really for slow stuff like this. Some buffers have 5v tollerent IO so be easier to use those on 3.3v etc even so 3v is enough to drive a high on 5v logic anyway. Some buffers are even 1 or 2ns type speeds. But I'd be inclined to not use such fast buffers on the cart port.

[AAG]

Thanks for replies so far.

Here's photo of what what I've got setup for basic test

20230924_145032.jpg

I solder on some pin headers on a cartridge PCB.

From cartridge, I'm feeding 5v, ground, and ROM4 select onto some breadboard.

Here's diagram (is there any good/free diagram creation tools?)

diagram.PNG

Hopefully with the photo/digram can see/imagine the jump wires from the broadboard to power trails/to cart pcb



My theory/what trying to get working

When ST resets/boots - TOS boot tries to read cart port (at various stages during boot).

I know I need some sort of tri-state level shifter/ttl non inverting buffer/line driver. (The SN74LVC245A came from "PI Hut as when looking for level shifter, that looked like it would do")

Initial test - can the above chip MIRROR the rom enable?
The logic analyser seems to always read high UNLESS its channel is connected to ground.
So thought is hard wire the input to tri-state to low/ground. Wire up the rom assert to chip select. Use analyser on ST chip select and chanel output from chip. They should match.

I've only got 22pf and 104pf ceramic caps at the moment - but I've tried using various combinations/non and they don't seem to make a differnce

Capture.PNG

I'll order up some different sized caps to try, but was wondering on opinions on
Is it (likely) not be be working as the bypass/decoupling caps aren't correct size?
(But due to pin positioning, its difficult to get cap between Vcc and ground.
The SN74LVC4245A (eg have vcc/ground above each other so bypass/decoupling cap attachment looks much easier.

is level shift correct thing to use?
Eventually will be 3.3 v to drive the tri-state chip, but wouldn't some sort of non inverting ttl buffer work?

Should anything be added to the rom select -> chip select? (Maybe a resistor on the 8inch wire?)

Is the bread board/wires just not up to the task?

Thanks

[exxos]

Caps in the pF range are no good. You need like 100nF ceramic at least and maybe 100uf electrolytic across power on the IC. For a test almost anying above 1uF should work.

A 74LS244 would be easier IMO. I'd also continuity check all connections as breadboard isn't great and you can endup with bad connections.