General Stuff(tm)

[stephen_usher]

Hmm... Still got a power-on reset problem on the STE after changing the caps. I couldn't find a suitable 10uF for C100 so used a 22uF, the same as C102.

Looks like it should be producing a ~400ms reset delay. That should be enough shouldn't it?

IMG_3183.jpeg

The top is C102.

[stephen_usher]

Swapping in a 56uF cap onto C102 fixes the problem and strangely switches the UBE switch on the Exxos ROM switcher to TOS 2.06 as opposed to 1.62 which it booted to before when the reset switch was hit.

The reset time is now 800ms.

[stephen_usher]

Curiouser and curiouser...

The machine is still not booting properly on power up, but only if the TOS 1.62 ROM is selected. Hitting reset and the machine works.

Switching to TOS 2.06 and the machine boots from cold every time.

What on Earth could cause that? Very strange.

@exxos any thoughts?

P.S. It doesn't get as far as reading the ROM as the diag cartridge doesn't run until the reset switch is hit. (When TOS 1.62 is selected.)

[exxos]

If it is the tos switching widget then the longer reset delay is likely switching it about on powerup. But I think I gave up with that chip because I don't think it was ever particularly stable. I think you should bypass the chip and used fixed jumpers and repeat your tests...

I have had odd things happen where only one particular tos versions works on power up . But I'm afraid I don't remember the outcome. I think mostly it is just down to bad connections either on the ROM or the jumpers etc

Look at all the seemingly bad reset problems I had with the DFB1 when it was a floating ROM pin.

[stephen_usher]

Fair enough. I can’t remember which OS is in the lower half of the ROM. I wonder if the UBE switch chip isn’t pulling the top address line low fast enough and it’s happening at an in opportune time during the CPU start-up.

[exxos]

Ironically..
viewtopic.php?p=65375#p65375

I thought I did something towards the reset circuit ages again. Probably one of those projects I simply run out of time for and ultimately forgot about.

By the sounds of it it was too small for jlc to do at the time but I think they can do small boards a lot easier now.

[stephen_usher]

How long does it have to hold the CPU in reset for?

Given I've been playing with MCP101 chips I'm wondering if an MCP100-450 would do the trick for power-on reset:

https://ww1.microchip.com/downloads/aem ... 11187f.pdf

[exxos]

How long does it have to hold the CPU in reset for?

It's not entirely that simple because the power supply startup time is the main issue, they are all different. Even on the same psu. One of those MCP chips may work. Basically you want a voltage supervisor reset chip. Where it automatically waits for the voltage to reach something like 4.8v , then have 100ms(ish) wait before reset goes high. I don't know what chip I used in the reset boad but I was likely thinking the same back then also.

The actual reset delay itself is probably not so important. If I remember rightly, the 68000 data sheet specified it needs to clock something like 100 clocks while reset is low to clear out and stabilise all it's internal registers before executing code. So on that basis something like 100ms is simple more than enough.

Basically it needs the "powergood" type circuit building which more modern PSUs have.

[stephen_usher]

Sounds precisely what the MCP100 does.

[stephen_usher]

After discovering the stash of Betamax videos at my Dad's house a couple of weeks ago I bought a Sony Betamax VCR from eBay...

It's being delivered by EVRI... Oh dear.

There may be a rebuild of a smashed video recorder thread coming up, if it arrives at all.