Megabus dimensions

[Badwolf]

Enough bodge wires?

IMG_0323.jpeg (750.37 KiB) Viewed 58 times

BW

[exxos]

starting to look like a proper project now!

[Badwolf]

Two steps forward, one step back.

Whilst I can't forment any memory test errors in normal operations, MiNT steadfastly refuses to run or be stable with DSTB1's AltRAM enabled in this configuration.

Not sure if it's a Megabusmaster or DSTB1 issue ATM, which makes debugging hard, but since DSTB1 is the only thing I have to test in it that has AltRAM, I'm left with a parallel debugging problem. Bah!

Of course I could break out a PiStorm, but I'm not sure that'd be gold standard for stability testing either!

The aim is, of course, to have a plain 68K and DSTB1 nice and happy in here to allow more extravagant things like PiStorm down the line.

BW

[alexh]

Keep at it. It looks fun. As a MegaST owner I'm curious to see what you come up with. Make some videos about it?

[Badwolf]

Quick update on this.

I'm quite happy with the way this works for the most part, but kept running into trouble with MiNT when AltRAM was enabled on DSTB1.

Following down the rabbit hole I found it was quite easy to trip up the processor (bus contention) when accessing AltRAM and also doing a lot of disc DMA work. MiNT is hard on the AltRAM hence MiNT could find the problem rapidly.

What I think it boils down to is that it's still the motherboard processor handling bus arbitration. There's no way to stop that that I can see. When the offboard processor is accessing AltRAM, it could be mid bus cycle and the motherboard processor just hands over the bus to the DMA chip (often only for a single access) and its access and the AltRAM access could contend the bus.

So I'm going for a respin with on-demand isolation of the two processors. This will have the downside that blitting into and out of AltRAM won't work any more (a big plus of 68k style AltRAM), but if it solves the problem, that's a small price to pay, IMO.

If the problem persists, then it must be something else going on.

Folded in the various bodge wires too. Dropped support for the GALs as I wouldn't be able to make this realistically work with them (was hoping it might be possible as a cost-reduced alternative). Also added in space for a secondary oscillator to experiment with dial-a-delay on the clock line.

Screenshot 2026-10-21 at 16.56.22.png (1.34 MiB) Not viewed yet

Fingers crossed for this one!

In the mean time I might try to get PiStorm going on the current prototype as I don't think background DMA will be a problem there. Internal processes on the PiStorm shouldn't drive the bus. OTOH it would need to honour bus arb, which I think is right at the bleeding edge ATM.

BW