Megabus dimensions

[exxos]

BTW is your Mega TOS board one of the end of life ones or will more be coming back into stock?

They are in my basket to order more. Just haven't pulled the trigger yet. Will try and do it later.

[Badwolf]

They are in my basket to order more. Just haven't pulled the trigger yet. Will try and do it later.

Cool. Ta.

BW

[Badwolf]

Have you tried just tying BR high and see if it gets to the desktop that way? The floppy drive won't obviously work but if it gets to the desktop reliably it can be an indication..

Good & quick idea. No, not yet. Very little other than combination testing so far.

Ah, rats. I completely forgot there is a fully functional on board processor which will honour those bus requests even if the external processor has its BR tied high.

That will definitely make things worse!

Time to break out the custom no-DMA emutos again, but that will only boot to CLI as will have to fit on a cartridge until the TOS boards are back.

BW

[Badwolf]

Time to break out the custom no-DMA emutos again.

I didn't have time to do much last night, but my no-DMA Emutos cartridge ran happily for an hour and a half last night.

It was doing absolutely nothing, of course. No mass storage and CLI only, but AFAIK the cursor flash is interrupt based.

So DMA looking the more likely now. Which does make sense really.

BW

[Badwolf]

I don't think it's the whole story, but I have found one glaring error. Not sure how to fix it just yet.

I've been fortunate in my mods so far that I've not tried to have two base 68000s going at the same time so hadn't thought about the synchronous bus system much. I should have done!

The E clock is only the second output pin that isn't quiescent during bus relinquishment (the other being BG, for obvious reasons). Putting a second 68000 in as is own bus master was leading to contention on the E line. Oops.

OK, so isolate the external CPU's E line, no problem. But now we're left with an asynchronous synchronous bus. This will obviously be a bit hit and miss and sure enough mouse and keyboard inputs are the bits that really fall by the wayside when DSTB1 kicks up to 16MHz.

I was thinking to isolate VPA from the external CPU as well and just have some kind of timing-based DTACK synthesised when the motherboard generates VPA, but VPA being visible to the CPU is required to indicate autovectored interrupts (VBL and HBL on the ST).

So I think my logic has to have its smarts upgraded to detect and facilitate autovectored interrupt cycles plus also do something about the newly asynchronous synchronous cycles.

So one step forward, two back. But a plan emerges.

BW


PS. I think the combined delay of the clock and the bus arb when DSTB1 is in the slot was too much and inverting the clock pushed things into the next cycle which is why I was seeing better results with an inverted clock. It may be version two needs its own oscillator and a set of jumpers to choose the delay to the clock to allow the user to fine-tune their skew. We'll see.

[exxos]

Ah I didn't even notice you had 2 CPU plugged in at once. I can confirm that doesn't work

Not sure I follow what you are exactly trying to do in the first place?