Falcon FPGA Core now on MiSTer

[Higgy]

Hi,

I don't think this has been posted:

https://misterfpga.org/viewtopic.php?t=10916

It would be nice if there is a SCSI HD Image with Falcon demos and games to see what the Falcon can do.
Someone posted a image with about 3 demos on.

I've seen here that Exxos has linked to an FTP with Falcon software. I guess I would need to use an emulator to get these files onto a HD image then put that onto the MiSTer.

[alexh]

Thanks for sharing. It says the chip set was verified against Hatari in Falcon mode but the description infers it is more than that. Perhaps a direct C-> HDL conversion of the Hatari logic?

I'll give it a go on Monday on my Superstation (MiSTer Clone)

[ijor]

Interesting, and impressive work. But to be honest, I'm not a fan of this approach. It should be the other way around. Software emulators should be based on FPGA cores. Not FPGA cores based on emulators. FPGA cores should try to reproduce the original hardware as closely as possible.

My philosophy is that an open source FPGA core reproducing legacy hardware should not only work well, it should also be an excellent preservation on how the original hardware was designed, not just how it behaved.

Still, an amazing work!

[Kochise]

Not FPGA cores based on emulators. FPGA cores should try to reproduce the original hardware as closely as possible.

Aren't emulators trying to reproduce the original hardware as closely as possible ?

Chicken, egg, ...

[ijor]

Aren't emulators trying to reproduce the original hardware as closely as possible ?

Not exactly. That would be very inefficient.

Emulators attempt to reproduce the original behavior as perceived externally to the emulator, but typically using completely different techniques. Hardware works in parallel. Software works sequentially. Not only that, modern processors benefit from caching and locality. Software can't efficiently process such things as sound and video one cycle at a time, as the hardware does. Then, emulators typically process video one scan line at a time, or may be even one frame at a time.

FPGA on the other hand, does work in parallel. Then the design can be rather close (not exactly identical though) to the original implementation. That's why I said in my previous message that an FPGA core should be modeled based on the original internal design, not only on the external behavior (as emulator typically are).

[Kochise]

I had this emulator in mind :

https://github.com/TomHarte/CLK

[mikro]

Well said @ijor. This is one of the reasons why I avoid MiST and its derivates: people have unrealistic expectactions what they really offer. They read "Atari/Amiga/whatever in FPGA" and almost automatically assume that it is a perfect replica of the original chipset. Which is rarely the case. So this "MiST world" lives in a bubble of its own bugs, quirks, inaccuracies, ... totally separate from emulators and most importantly, real hardware.

[ijor]

I had this emulator in mind :
https://github.com/TomHarte/CLK

I'm not familiar with that particular emulator so I can't comment much about it. But I'm familiar with Hatari (which is the one that this Falcon core seems to be based), and with several other emulators. Every single one I know works more or less as I described. Otherwise it would be more a simulator than an emulator, which could be accurate to the transistor level, but awfully inefficient in terms of speed.

[alexh]

one of the reasons why I avoid MiST and its derivates: people have unrealistic expectations what they really offer. They read "Atari/Amiga/whatever in FPGA" and almost automatically assume that it is a perfect replica of the original chipset. Which is rarely the case.

It does depend on the core. Some cores are implemented using the original design files (tweaked for FPGA) or from decapped chips. But yes a lot of them are guesses. Typically using ideas taken from software emulators.

[Kochise]

Typically using ideas taken from software emulators.

That's the idea, emulators and not simulators, because the underlying CPU isn't necessarily powerful enough to "simulate" the target hardware.

Same for FPGA, the gates are not necessarily "simulating" the target hardware on a 1:1 basis, because not enough cells, or no original netlist to base the design on, etc.